Lauro Rizzatti is a verification consultant. He was formerly general manager of EVE-USA and its vice president of marketing before Synopsys’ acquisition of EVE. Previously, he held positions in management, product marketing, technical marketing, and engineering. He can be reached at … More »
May 27th, 2015 by Lauro Rizzatti
Emulation is enjoying its moment in the spotlight and none too soon. Design complexity of all types has conspired to make chip verification an arduous task. These days, the fabric of system-on-chip (SoC) designs includes several processing cores, large sets of specialized IP, a plethora of peripherals and complex memories, routinely pushing the design size into the hundreds of million gates. Embedded software now exceeds the complexity of the hardware.
Consider that for each hardware designer there are at least five software developers. No surprise that chip verification and validation has become an overriding concern for all project teams, particularly when hardware and software integration is concerned. Here is where the rubber meets the road, and where the verification challenges reach their peak.
May 15th, 2015 by Oliver Bell
What’s the DVContinuum?
For more than 25 years, DVCon is the premier conference to discuss challenges and achievements for Functional Design and Verification of Electronic Systems and Integrated Circuits. The DVContinuum includes the well-established DVCon United States in March, augmented with DVCon India in September and DVCon Europe in November (Munich, Nov 11 – 12, 2015).
For each region, DVCon provides a well-chosen mixture of technical paper sessions, tutorials, key notes, posters and exhibits. Sponsored by Accellera Systems Initiative, DVCon attendees get access to the latest information on various Accellera Standards and its application for system-level design, modelling and verification (including UVM, SystemC, SystemVerilog, IP-XACT and many more). The topics include system-level virtual prototyping, IP reuse, design automation, mixed-signal design, low power design and verification. Facilitating DVCon not only in the US but also in Asia and Europe allow networking and discussions in a much broader audience and expand DVCon’s value to wider community than those only who have the opportunity to travel to the US.
If you like to share your experience with the DVContinuum, submit your paper: DVCon Europe deadlines are May 11th for your draft paper and June 1st for your Tutorial submission. More info: http://dvcon-europe.org (India: http://dvcon-india.org/ US: http://dvcon.org/ )
The DVContinuum Anno 2015 – a Historic Perspective
As DVCon attendee, you will hear a lot about “shift left” and early verification of complex systems. This is not a new concept at all, even it may look like today. A very epic example for a historic shift left had been called out by John F Kennedy in May 1961: “I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the moon and returning him safely to the earth.” At that time, the required technologies and procedures for a moon landing did not even exist.
April 22nd, 2015 by Anne Cirkel
Times are good in EDA. 2014 was a record revenue year for our industry, according to an April 13 EDAC announcement. Several technology areas (IC physical design and semiconductor IP) and geographies (the Americas and Asia-Pacific) experienced double digit growth in Q4. The number of people working in EDA is on the rise, too: a total of 31,735 employees at companies EDAC tracks in Q4 2014, compared to 29,880 employees a year earlier. This rising tide is lifting all boats — including #52DAC, which I invite you to register for today if you haven’t already.
March 19th, 2015 by Anne Cirkel
Nose around the design automation industry a bit and you’re sure to find mention of the goal to “shift left.” Basically the idea is to try to solve problems and add value earlier in the design cycle. Engineers usually first stitch together basic functional blocks of whatever they are building before moving on to higher level system integration and software tasks. Turns out this isn’t a bad metaphor for conference planning. Like chips and ICs, conferences work best when the essential elements (in this case, marquee presenters and core technical content) are in place early. I can safely report this is more or less true now for DAC 52—which is slated to be simply amazing when it’s finally “launched” this summer.
DesignCon Panel On Next – Gen Engineering has our young engineers voicing their opinion on the future of engineering
March 4th, 2015 by Shachi Nandan Kakkar
DesignCon, held at the Santa Clara Convention Center, is one of the biggest annual conference on product technologies, design methodologies, and EDA software, with a focus on system-on-chip design.
February 11th, 2015 by Anne Cirkel
In tech it’s hard to avoid the conclusion that you’re either growing or dying, on the way up or on the way out. I poked modest fun at Apple in an earlier post, but their latest financial results certainly illustrate the point. By now you’ve probably heard that Apple’s $18 billion quarterly profit was the largest ever reported by a public company. At DAC, we may not be selling 34,000 iPhones per hour around the clock for three straight months (wow!), but we are setting our own records.
January 9th, 2015 by Anne Cirkel
Technical conferences change over time. Consider CES, wrapping up now in Las Vegas after generating the expected spate of headlines, mostly about wearables. (I have a Pebble so I can safely claim to be on the cutting edge, or at least the bandwagon.) For starters is the issue of the conference name. You won’t see many references to the “Consumer Electronics Show” on the official conference site this year. Consistent with tech’s global ambitions and love of acronyms, the official handle now seems to be “International CES,” though the media doesn’t seem to have caught onto this yet. More significant is how content at CES has evolved, even recently. As recently as 2011, the show reliably featured a slew of new Android phones. Now, most of the big announcements about smartphones — I think there is little argument these are still the hottest consumer devices on the planet — take place at Mobile World Congress in Barcelona.
December 10th, 2014 by Sanjay Gangal
What drives what happens now? A critical combination of the latest technology and knowledge, which is what you’ll find at IPC APEX EXPO 2015.
November 22nd, 2014 by Anne Cirkel
Thanksgiving is here so it’s likely to be a slow week in the EDA industry. Of course, like much else in our culture, this event has been co-opted by rampant media messages to shop and consume. Already I’ve seen lots of stories about Black Friday, mostly discussing whether the whole idea of a 24-hour window is now moot given Cyber Monday and the reality that the holiday shopping season now starts right after Halloween and stretches into January.
As a German I know I must tread lightly when writing about the most American of holidays. Turkey is not all that big on holiday menus back home and as I’ve written about in an earlier EDA Café post, football (or rather fussball) will always mean something different to me, no matter the success of the regional favorite Seahawks or my staff’s obsession with making their weekly fantasy picks. I’ll just say that I’ve grown to like some of the old-fashioned aspects of the holiday (a good meal with friends followed by a hike with the dogs, who demand to get out regardless of the weather). I can’t help but being thankful that EDA is not part of this annual shopping lunacy, at least not directly. Last I looked, the big three EDA vendors aren’t offering holiday-themed sales and I’ve never yet seen a line out the door for a piece of technical software. (That said, DAC attendees have been known to queue up for the free coffee, beer and wine that exhibitors offer almost every day — as I see it, much more reasonable behavior than waiting outside a superstore before it opens.)
November 4th, 2014 by Anand Shirahatti
Initially, USB provided two speeds (12 Mbps and 1.5 Mbps). With rapid adoption and success of the USB standard and the increasing power of PCs and computing devices, the USB 2.0 specification was defined in the year 2000. USB 2.0 provided upto 480 Mbps of bandwidth while keeping software compatibility with earlier USB applications. With ever increasing bandwidth requirements, in 2008 the USB 3.0 specification (providing 5 Gbps bi-directional bandwidth) was released. USB 3.1 is the next logical step in this progression. It provides 10Gbps of bi-directional bandwidth while maintaining backward compatibility with previous USB versions. To know more about USB 3.1 Verification solution click here.
In this post, we will analyze the technical differences between the USB 3.1 and USB 3.0 specifications. The aim is to enable people familiar with USB 3.0 to quickly understand the main aspects of USB 3.1.
We will analyze the PHY, Link and Protocol layers and list out the major ways in which USB 3.1 differs from USB 3.0.