Oliver Bell has over 20 years of experience in semiconductor industry (Siemens, Synopsys, Ericsson, Micronas, INTEL), with focus on the development and rollout of advanced pre-silicon verification methodologies and prototyping for complex SoC in communication and consumer applications. Oliver … More »
Experience the DVContinuum
May 15th, 2015 by Oliver Bell
What’s the DVContinuum?
For more than 25 years, DVCon is the premier conference to discuss challenges and achievements for Functional Design and Verification of Electronic Systems and Integrated Circuits. The DVContinuum includes the well-established DVCon United States in March, augmented with DVCon India in September and DVCon Europe in November (Munich, Nov 11 – 12, 2015).
For each region, DVCon provides a well-chosen mixture of technical paper sessions, tutorials, key notes, posters and exhibits. Sponsored by Accellera Systems Initiative, DVCon attendees get access to the latest information on various Accellera Standards and its application for system-level design, modelling and verification (including UVM, SystemC, SystemVerilog, IP-XACT and many more). The topics include system-level virtual prototyping, IP reuse, design automation, mixed-signal design, low power design and verification. Facilitating DVCon not only in the US but also in Asia and Europe allow networking and discussions in a much broader audience and expand DVCon’s value to wider community than those only who have the opportunity to travel to the US.
If you like to share your experience with the DVContinuum, submit your paper: DVCon Europe deadlines are May 11th for your draft paper and June 1st for your Tutorial submission. More info: http://dvcon-europe.org (India: http://dvcon-india.org/ US: http://dvcon.org/ )
The DVContinuum Anno 2015 – a Historic Perspective
As DVCon attendee, you will hear a lot about “shift left” and early verification of complex systems. This is not a new concept at all, even it may look like today. A very epic example for a historic shift left had been called out by John F Kennedy in May 1961: “I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the moon and returning him safely to the earth.” At that time, the required technologies and procedures for a moon landing did not even exist.
For a successful moon mission, not only the actual rocket science engineering but thorough and early verification, continuous learning by the teams and stress testing using system simulation vehicles were key factors. Looking deeper into the story of the successful Apollo 11 landing on July 20, 1969, we get very interesting insights on the importance of the right verification. As the lunar module Eagle made its landing approach to the moon, in short distance to the surface, among other related ones a computer alert 1202 was raised. Steve Bales, the computer expert in Gene Kranz’s Mission Control team, was able to analyze the alert 1202 quickly as an “executive overflow” alarm. This simply meant that the computer was in trouble completing its work in the available cycle time. So the right GO for landing decision was made, and no ABORT with maybe fatal consequences. Because exactly this test case was simulated upfront the Apollo 11 mission, Steve Bales was able to correctly analyze this alert so fast. Just two weeks prior to the Apollo 11 launch, simulation supervisor Dick Koos had thrown in a series of program alarms (including the 1202) during the integrated simulations for the stress testing of the flight controllers and the Apollo 11 crew’s reaction. During this massive testing, the team had failed with the wrong ABORT decision – two weeks later this simulation experience became real and helped Mission Control for the right decision and supported a successful moon landing.
As you may see from this historical example, the DVContinuum addresses the ever increasing complexity, which was well mastered 50 years ago, and exemplifies the importance for our IC industry. Understanding this DVContinuum is vital to meet the requirements and to address the complexity of the “Systems of Systems” verification. Smarter abstraction techniques, automation, stimuli techniques and above all the creativity of Verification Engineers to create the appropriate simulation models in a very efficient way, will help to continuously shift the limits of verification.
If you are interested to experience the DVContinuum yourself, join us at DVCon Europe and see great examples of yesterday’s, today’s and tomorrow’s systems. Looking forward to meeting you in Munich!