Lauro Rizzatti is a verification consultant. He was formerly general manager of EVE-USA and its vice president of marketing before Synopsys’ acquisition of EVE. Previously, he held positions in management, product marketing, technical marketing, and engineering. He can be reached at … More »
Survivor’s Guide to Hardware Emulation at DAC
May 27th, 2014 by Lauro Rizzatti
It wasn’t all that long ago when hardware emulation providers heading to DAC worked overtime to get their booths filled with interested verification engineers with big challenges. Hardware emulation was still viewed as an esoteric and expensive luxury that only few could afford.
Fast forward to 2014. This year is prime time for hardware emulation, now a mandatory verification approach for all semiconductor designs. Left alone are a few analog-centric designs and a bunch of small digital designs. It is also become somewhat more affordable based on the price per gate.
I predict this year DAC will be much different than previous years as semiconductor companies, forced to accelerate time to market even as their chip designs get increasingly more complex, are looking to hardware emulation.
Good news for the hardware emulation vendors. Charting the waters of hardware emulation can be daunting, however, so here’s a survivor’s guide to where to go during DAC to see the most popular and effective hardware emulation platforms.
Step inside the DAC exhibition hall turn right and walk to the end of the hall, turn left and you’ll see Cadence three booths in. Booth #2616 will be unmistakable because it’s 5,000 square feet of floor space and its Palladium hardware emulator as big as a refrigerator will be in a visible spot. That’s because it has earned the king’s crown for the most popular emulator over the past decade with a wide-ranging set of capabilities that its competitors could not match.
The processor-based Palladium-XP2 still reigns for fastest compilation time, flexible design debugging and support for several concurrent users. If your design team has a large budget, an equally complex design and a short window to get it verified, Cadence’s Palladium may be for you.
If you wish to learn more about Palladium-XP2, ask for Frank Schirrmeister, Cadence’s group director, product marketing, System Development Suite.
Leaving Cadence and walking right and counterclockwise, head to the end of the hall, turn left and there will be Mentor Graphics in Booth #1733, four booths in. Mentor’s bullish on hardware emulation these days, and will surely and visibly demonstrate Veloce2 in its 3,000 square foot booth.
Based on an evolution of its Crystal2 emulator-on-chip design, Veloce2 closed the gap with Palladium. With its newly announced OS3, Veloce2 has all that it takes to capture the center seat. It has a comprehensive feature set meeting any design capacity with the fastest transaction-based performance and its inclusive hardware verification and software validation capabilities make it ideal for creating large enterprise verification platforms. If you develop SoC designs rich in embedded software, Veloce2 may be the right choice.
To learn more about Veloce2, look for Jim Kenney, director of marketing for Emulation, in the Mentor booth.
Three booths to the right of Mentor and along the back wall is Synopsys in Booth #1133 in 2,400 square feet. Its emulation system is called ZeBu for Zero Bugs. Synopsys launched ZeBu-Server3 in February 2014.
Claimed to offer the largest design capacity in the smallest footprint in the industry, it also runs at a faster clock speed than its competitors. For software validation, it may be recommended.
If you wish to learn more about ZeBu-Server3, ask for Tom Borgstrom, director of the Verification Group at Synopsys.
I’m only scratching the surface in this blog. For a more comprehensive analysis of the three choices, watch for my article that will be posted on EE Journal May 29 … just in time for DAC.