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 Guest Blogger
Rob van Blommestein
Rob van Blommestein
EDA Consortium Communications Chair and Director of Corporate Communications at Jasper Design Automation.

Jasper Users Share Their Knowledge for Applying Formal Across the Entire Design and Verification Flow

October 30th, 2013 by Rob van Blommestein

This year’s Jasper User Group Meeting was found to be a great melting pot of design and verification experience and knowledge. Users from all over the globe met for the 2 day conference on October 22 and 23 to discuss the innovative ways they are using Jasper Formal solutions to attack their design and verification challenges. What experiences did Jasper users share? The Jasper User Group boasted 14 user presentations from the following companies on the following topics:

  • ARM
    • How Formal Verification Can Please Your Project Manager (too)
    • The Pelican Has Landed: Mainstream Formal on the Pelican Processor
    • Productivity Gains in Multi-core SoC Connectivity Verification
    • Chip-Wide Clock Gating Verification Using Jasper’s SEC App
    • Leveraging JasperGold® for Efficient Reset Design and Verification
  • Broadcom
    • Less Is More: How We Learned to Avoid Over-Constraining
    • Back to the Future with Formal Scoreboarding (best paper winner)
    • Case Studies Using the XProp Formal App to Detect ‘X’ Optimism Related RTL Bugs
  • Samsung: Automated Interrupt Discovery/Verification Flow
  • Juniper
    • Formal Verification: The First Line of Defense
    • BIST Connectivity Verification
  • Ericsson: Connectivity Checking
  • APM: Everything I Wish I Knew When I First Started “Jasperizing” But Didn’t Know to Ask
  • Sony: Applying Formal Verification to Timing Generation Block

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Category: Jasper

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