This year’s Jasper User Group Meeting was found to be a great melting pot of design and verification experience and knowledge. Users from all over the globe met for the 2 day conference on October 22 and 23 to discuss the innovative ways they are using Jasper Formal solutions to attack their design and verification challenges. What experiences did Jasper users share? The Jasper User Group boasted 14 user presentations from the following companies on the following topics: (more…)
Archive for October, 2013
Jasper Users Share Their Knowledge for Applying Formal Across the Entire Design and Verification FlowWednesday, October 30th, 2013
Every now and then I meet somebody (compiler writers most of the time, but not only) who believes that generating human-readable RTL code is worthless. They claim that nobody should need to look at generated code, among other things because they should just trust the compiler, like software engineers do. It is time to examine the facts.
1. The majority of the hardware engineers that we’ve met with Synflow want to be able to understand the generated RTL, because they want to be able to reuse, verify, optimize or modify the generated code themselves. This includes people from big companies such as STMicroelectronics, Samsung, Renesas, ARM, as well as medium enterprises like Thomson Video Networks, RivieraWaves, ScaleoChip. Although this is only a subset of all hardware designers and semiconductor companies, I think we can consider it a reasonably representative sample. As a matter of fact, the rest of designers may not care whether the generated code is human-readable, but no designer has ever told us that he or she would prefer incomprehensible code, or even worse a netlist. Actually, that is probably because… (more…)