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Matthieu Wipliez
Matthieu Wipliez
Matthieu Wipliez is CTO and co-founder of the Synflow EDA start-up company. He has spent the last two years working on a new programming language called C~ ("C flow") for next-generation hardware design, and developing an IDE for that language. Matthieu writes about what he loves, like disruptive … More »

Bitcoin mining IP core with Synflow Studio

 
September 15th, 2013 by Matthieu Wipliez

To design an ASIC Bitcoin miner, the first thing you will need is a Bitcoin IP core, a piece of silicon that performs a double SHA-256 (if the previous sentence is Klingon to you, I’d advise you to read the gentle introduction to Bitcoin mining). You can buy a SHA-256 IP from numerous IP vendors on the net, you can also find one free of charge on OpenCores. Or you can design one yourself. If you are aware of what’s wrong with RTL, or you know that High-Level Synthesis might not help you much, or you are an innovator, and/or simply you just want to see what Synflow Studio can do, keep reading!


First, you can take a look at the videos in this post or on our YouTube channel, where I show how to get started with Synflow Studio, create the main loop of SHA-256, and complete and test the IP. You can read the C~ code (as well as the VHDL and Java code generated by Synflow Studio) on our Github repository, where the IP is under MIT license. Keep in mind that at this point (commit 5f5f25131a…) I have only written a behavioral description of the IP, which mainly consists of a straightforward implementation, kind of a copy-paste from the FIPS 180-4 standard. My implementation only hashes one block, and currently its performance is limited:

  1. The IP is not pipelined, so it spends 64 cycles to compute W, but this could be done in parallel to the main loop.
  2. The ‘K’ constant array should be moved to its own task to ensure proper inference as a synchronous ROM. Doing so will require scheduling the reads of ‘K’ one cycle in advance, because a synchronous ROM by definition has a 1-cycle latency.
  3. The ‘W’ array should be implemented as a RAM rather than as a register-based array. Doing so will require additional registers: the computation of W[t] is dependent on four values, W[t – 2], W[t – 7], W[t – 15], W[t – 16], but we can only do one read per cycle.
  4. Finally, we’ll need to extend the implementation to handle multi-block messages, but this should be trivial.

Implementing all of this will the subject of a future post or video.

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