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 Guest Blogger
Rob van Blommestein
Rob van Blommestein
EDA Consortium Communications Chair and Director of Corporate Communications at Jasper Design Automation.

Get Powered Up with Formal Low Power Verification!

March 11th, 2013 by Rob van Blommestein

We as consumers want more functionality from our electronic devices whether from our smart phones or household appliances.  The problem that we create from these functionality demands is not only an increase in power consumption, but also a significant increase in complexity for how the power in these devices is managed.  We as consumers don’t often think about these consequences, but your typical electronic design engineer certainly does.

Today’s electronic designs require that power management and reduction be a central concern throughout the chip design flow from architectural design to RTL implementation and physical design.  The power verification dilemma is two-fold.  Not only must the design and verification engineer address whether or not the inserted power management circuitry functions correctly, but also that the overall chip functionality is not corrupted by the power intent described in the UPF or CPF descriptions.

Functional analysis, optimization and verification throughout the design flow, complicated by inadequate visibility of third-party IP white-box functionality, mandates the following five principal requirements for implementing and verifying a low power scheme.

  1. Sufficiently accurate power estimates using representative waveforms, both pre-and post-rout.
  2. Accurate visibility and analysis of the white box behavior of third-party IP prior to its modification and reuse.
  3. The deployment and ongoing optimization and verification of appropriate power reduction techniques, both pre- and post-integration.
  4. Exhaustive functional verification at the architectural and RTL levels, both before and after the deployment of power optimization circuitry.
  5. Verification of hardware functionality compliance with software control sequences.

Traditional power-aware verification has been done with a patchwork of tools and approaches that only provide limited analysis and verification capability resulting in inadequate quality of results (QoR).

The JasperGold Low Power Verification App and flow comprehensively meets power-aware verification requirements with the requisite QoR.  The Low Power App automatically creates power-aware transformations and automatically generates a power-aware model that identifies power domains, power supply network and switches, isolation rules and data retention rules.  It does so by parsing and extracting relevant data from the UPF/CPF specification, the RTL code and any user-defined assertions.  It then automatically generates assertions that can be utilized by other JasperGold Apps to verify that the power reduction and management circuitry through out the design (architectural features, unfamiliar RTL blocks, RTL functionality, power management circuitry, control and status register specification, equivalency before and after power management insertion, X’s, and RTL connections) conforms to the UPF/CPF specification and does not corrupt the original RTL functionality.

To learn more about formal methods for low power verification download the white paper “Formal Verification of Power-Aware Designs Using the JasperGold Low-Power Verification App” at

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