We as consumers want more functionality from our electronic devices whether from our smart phones or household appliances. The problem that we create from these functionality demands is not only an increase in power consumption, but also a significant increase in complexity for how the power in these devices is managed. We as consumers don’t often think about these consequences, but your typical electronic design engineer certainly does.
Today’s electronic designs require that power management and reduction be a central concern throughout the chip design flow from architectural design to RTL implementation and physical design. The power verification dilemma is two-fold. Not only must the design and verification engineer address whether or not the inserted power management circuitry functions correctly, but also that the overall chip functionality is not corrupted by the power intent described in the UPF or CPF descriptions.