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Rob van Blommestein
Rob van Blommestein
EDA Consortium Communications Chair and Director of Corporate Communications at Jasper Design Automation.

Jasper Users Share How They Upgraded Their Verification with Jasper

August 1st, 2012 by Rob van Blommestein

Enough can’t be said about the power to educate based on experience.  At this year’s DAC, a few of Jasper’s top users volunteered to give seminars on their best practices for using Jasper Formal technology.  If you happened to miss DAC or did attend but didn’t get a chance to visit the Jasper booth, here’s your chance to view the on-line videos from ST, ARM, and NVIDIA on how they utilized Jasper Formal technology to get ahead in their designs.

ST: Low Power Verification and Optimization with Jasper Formal

ST Microelectronics talked about the verification challenges associated with sophisticated low-power designs, and ways those challenges are being addressed by Jasper’s power-aware formal verification technology.  The seminar detailed how Jasper’s low-power verification solution applies to:

  • Parsing CPF information to enable power-aware formal analysis
  • X-propagation due to shutting down power
  • Functional impact due to power-down
  • Power-up state analysis
  • Exploration of power-state

ARM: Multi-processor Verification Success with Jasper Formal – The Proof Is in the ROI

ARM’s Cortex multi-processors provide advanced power management and performance for the next generation electronic designs.  In this seminar, ARM discussed how Jasper’s advanced formal technology helped to verify a variety of issues that significantly improved time-to-market.  Details were be given on how Jasper was integrated into ARM’s overall verification flow so that bugs found using Jasper formal could be tracked and the ROI measured.  Examples were shown on how Jasper formal technology was used to find more bugs in less time and provide more stabilization in the verification effort.  The seminar also explored how Jasper is partnering with ARM to utilize formal technology on future projects for mitigating design and verification risks.

Nvidia: Sequential Equivalency Checking for Power Optimization

Nvidia faces critical verification challenges involving designs such as a GPU Streaming Multiprocessor, SIMD processor and a complex instruction set for graphics and compute.  Among the verification challenges that Nvidia must overcome is sequential equivalence checking.  This two-part seminar began with Nvidia discussing their methodology for sequential equivalence checking of two RTL models.  Examples of how JasperGold was used to verify the correctness of clock gating optimization were shown as well as the results of how this methodology enabled higher verification coverage and identification bugs not found with dynamic methods.

The second half of the seminar focused on the use of Jasper’s prototype JasperGold App for sequential equivalence checking on one of Nvidia’s most complex blocks.  Results showed that performance was far superior to any other solution evaluated by Nvidia including commercial sequential equivalence checking tools and model checking tools that provide sequential equivalence checking capabilities.  A roadmap for the availability of the JasperGold Sequential Equivalence Checking App was also shared.

To register to view any of these seminars, go to

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