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Mark Waller, VP of Research and Development, Pulsic
Mark Waller, VP of Research and Development, Pulsic
Mark is the co-founder and Vice President of Research and Development at Pulsic, and was a key Developer and Project Leader of IC Place and Route Research at Zuken-Redac Systems Limited.

What Will It Take for Next-generation Routing to Meet the Needs of the Most Advanced Process Nodes and Beyond?

 
June 1st, 2010 by Mark Waller, VP of Research and Development, Pulsic

Custom chip designers are reluctant to adopt automation, largely because they have been traditionally better able to design by hand. While hand crafting may still suffice for designs of relatively few transistors, it is no longer sufficient for the new, highly complex devices that are becoming the norm.

At advanced nodes, process rules make full hand layout almost impossible. For example, instead of simple space rules, “space” now depends on the width of metal and the length of parallel lines, and there are complex via and contact density rules and end-of-line rules that can’t readily be dealt with by hand crafting. An automatic custom design routing tool that can deal with the new custom world will improve productivity and achieve on-time, efficient design delivery.

The thought of automation raises the specter, with some designers, that they, or the majority of their functions, will be replaced. However, increased custom design automation will increase the productivity of designers, not replace them, as we have seen in the digital design world. Given that extremely complex projects now need to be completed in the same time and with the same number of people as older, simpler designs, automating the custom design process to increase the productivity of designers is the only way to manage multi-thousand-gate designs.

The list of “must haves” for today’s routing technologies includes more flexibility, adherence to multiple process rules, and faster performance. A router should allow arbitrarily-shaped cell row regions to be generated for arbitrarily-shaped cells, and let them be continuously reshaped and developed for optimum area efficiency. It should also offer specialized routing functions for extreme-aspect-ratio designs. The routing engine needs to complement the skills and knowledge of an experienced layout designer. Interactive and semi-automatic editing features that are correct by construction should, at minimum, provide an on-line DRC capability, allowing layout designers to complete manual routing operations error-free and DRC-correct every time. Alternatively, the router can cut layout time by automating the entire layout procedure. And, finally, as with Pulsic’s UniRoute™, which offers all these capabilities, it should be production-proven at the most advanced nanometer process nodes.

The industry has learned from the 65nm and 45nm experience that process rules for advanced nodes have reached a degree of complexity that is impossible to handle within existing resource constraints through manual design. The requirements of emerging custom designs will increase the need for simultaneous and automated routing of analog and digital nets within the same design, using the same technology, features, and database for the entire design environment. Eliminating the need for, and cost of, separate tools while also enabling custom design automation and high-capability routing will ensure that custom designers can meet the needs of advanced process nodes.

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