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Archive for June, 2010

Accellera at DAC: Defining a Universal Verification Methodology

Monday, June 7th, 2010

First of all, we’d like to invite all the DAC attendees to Accellera’s breakfast and panel about UVM: Charting a New Course on Tuesday, June 15, 7:30 am – 9:00 am, Room 203B in Convention Center.

It is no news when one talks about increasing complexity of designing the SoC devices. It is a foregone conclusion that designing is a relatively bounded problem compared to verification. Just as design reuse through Semiconductor IP (aka design IP) helped bring the designers up the productivity curve, in the last decade Verification IP (VIP) has done the same for the verification engineers. Two leading methodologies, Verification Methodology Manual (VMM) and Open Verification Methodology (OVM), helped accelerate the adoption of structured verification methodologies using SystemVerilog as well as the creation of commercially available verification IP to independently validate integration of design IP in SoCs. Essentially, both methodologies are a collection of SystemVerilog classes with inherent semantics for their behavior in different phases of the simulation. The user creates verification objects from these classes and attaches them to the design components as traffic/data generators, monitors, checkers, etc.


What Will It Take for Next-generation Routing to Meet the Needs of the Most Advanced Process Nodes and Beyond?

Tuesday, June 1st, 2010

Custom chip designers are reluctant to adopt automation, largely because they have been traditionally better able to design by hand. While hand crafting may still suffice for designs of relatively few transistors, it is no longer sufficient for the new, highly complex devices that are becoming the norm.

At advanced nodes, process rules make full hand layout almost impossible. For example, instead of simple space rules, “space” now depends on the width of metal and the length of parallel lines, and there are complex via and contact density rules and end-of-line rules that can’t readily be dealt with by hand crafting. An automatic custom design routing tool that can deal with the new custom world will improve productivity and achieve on-time, efficient design delivery.

The thought of automation raises the specter, with some designers, that they, or the majority of their functions, will be replaced. However, increased custom design automation will increase the productivity of designers, not replace them, as we have seen in the digital design world. Given that extremely complex projects now need to be completed in the same time and with the same number of people as older, simpler designs, automating the custom design process to increase the productivity of designers is the only way to manage multi-thousand-gate designs.


TrueCircuits: IoTPLL

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