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 The Dominion of Design
Graham Bell
Graham Bell
Graham is Sr. Director of Marketing at Real Intent. He has over 20 years experience in the design automation industry. Occasionally he writes blogs for the Dominion of Design. The views and opinions expressed in this blog are his alone and not those of his employer. Knowledge Center: 2½D Integrated Circuits

January 28th, 2011 by Graham Bell

Wednesday, January 26, 2011
By: Paul McLellan / Green Folder
Topic: Back-End — Sub-topic: New Technologies and Directions


This is an overview of the current state of 3D chips, or, in particular what has become known as 2½ D chips based on silicon interposer technology using through-silicon vias (TSVs). It is based on the keynotes at the 3D architectures for semiconductor integration

Article Text

The first thing to note is the 3D chips do seem to be happening after many years of being like gallium arsenide, just a year or two more. There are designs in production, there are lots of pilot projects and the ecosystem (in particular, who does what) seems to be starting to fall into place.

The first approach to talk about is flipping one chip and attaching it to the top of another. This is done by creating bonding areas on each chip, growing (usually copper) microbumps to create die-die interconnect at a pitch of approximately 50um. The big user of this technology is in digital camera chips. The CCD image sensor is actually thinned to the point that it is transparent to light and then attached to the image processing chip. The light from the camera lens passes through the silicon to the CCD unobstructed by interconnect etc which is all on the other side of the sensor.

This approach is also used for putting a flipped memory chip onto a logic chip (see figure 1). It is not well-known, but the Apple A4 chip is built like this, with memory on top of the processor/logic chip. There are now standardization committees working on the pattern of microbumps to use for DRAMs (analagous to standard pinout for DRAMs) so that DRAM from different manufacturers should be interchangeable. Unlike in the picture, the bumps are all towards the center of the die so that the pattern is unaffected by the actual die size which may differ between manufacturers and between different generations of design.

Although this technology is formally 3D, since there are two chips, it doesn’t require any connections through any chips and is a sort of degenerate case.
The key technology for real 3D chips is the through-silicon-via (TSV). This is a via that goes from the front side of the wafer (connecting to one of the metal layers) through the wafer and out the back. The TSV is typically about 5-10um across and goes about 8-10 times its width in depth, so 50-100um. A hole is formed into the wafer, lined with an insulator and then filled with copper. Finally the wafer is thinned to expose the backside. Note that this means that the wafer itself ends up 50-100um thick. Silicon is brittle so one of the challenges is handling wafers this thin both in the fab and when they have to be shipped to an assembly house. They need to be glued to some more robust substrate (glass or silicon) and eventually separated again during assembly. The wafer is thinned using a type of CMP (chemical mechanical polishing, similar to how planarization is done between metal layers in a normal semiconductor process) until the TSVs are almost exposed. More silicon is then etched away to reveal the TSVs themselves.

Figure 2 shows Samsung’s approach. FEOL (which means front-end of line which means transistors and is nothing to do with front-end design) is done first. So the transistors are all created. Then the TSVs are formed. Then BEOL (which means back-end of line which means interconnect and is nothing to do with back-end design). After the interconnect is done then the microbumps are created. The wafer is glued to a glass carrier. The back is then ground down, a passivation layer is applied, this is etched to expose the TSVs and then micropads are created. This approach is known as TSVmiddle since the TSVs are formed between transistors and interconnect. There is also TSVfirst (build them before the transistors) and TSVlast (do them last and drill them through all the interconnect as well as the substrate).

There are two design issues with TSVs. First is the exclusion area around them. The via comes up through the active area and usually through some of the metal layers. Due to the details of manufacturing, quite a large area must be left around the TSV so that it can be manufactured without damaging the layers already deposited. The second problem is that the manufacturing process stresses the silicon substrate in a way that can alter the threshold values of transistors anywhere nearby, thus altering the performance of the chip in somewhat unpredictable ways.
There are two classes of true 3D chips which are being developed today. The first is known as 2½D where a so-called silicon interposer is created. The interposer does not contain any active transistors, only interconnect and decoupling capacitors, thus avoiding the issue of threshold shift mentioned above. The chips are attached to the interposer by flipping them so that the active chips do not require any TSVs to be created. True 3D chips have TSVs going through active chips and, in the future, have potential to be stacked several die high (first for low-power memories where the heat and power distribution issues are less critical).

The active die themselves do not have any TSVs, only the interposer. This means that the active die can be manufactured without worrying about TSV exclusion zones or threshold shifts. They need to be microbumped of course, since they are not going to be conventionally wire-bonded out.

Figure 3 shows four die bonded to a silicon interposer using microbumps. There are metal layers of interconnect on the interposer, and TSVs to get through the interposer substrate to be able to bond with flip chip bumps to the package substrate. Flip-chip bumps are similar to micobumps but are larger and more widely spaced.

In fact figure 3 is an actual production Virtex-7 FPGA from Xilinx. They call the technology “stacked silicon interconnect” and claim that it gives them twice the FPGA capacity at each process node. This is because very large FPGAs only become viable late after process introduction when a lot of yield learning has taken place. Earlier in the lifetime of the process, Xilinx have calculated, it makes more sense to create smaller die and then put several of them on a silicon interposer instead. It ends up cheaper despite the additional cost of the interposer because such a huge die would not yield economic volumes.

The Xilinx interposer consists of 4 layers of 65um metal on a silicon substrate. TSVs through the interposer allow this metal to be connected to the package substrate. Microbumps allow 4 FPGA die to be flipped and connected to the interposer. See the picture to the right. An additional advantage of the interposer is that it makes power distribution across the whole die simpler. This seems to be the only design in volume production today.
Paul McLellan is an independent consultant, blogger at and Managing Editor of the DAC Knowledge Center.

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Letter from the Chairman of Si2 and Member Report 2010

January 21st, 2011 by Graham Bell


Prabhakaran Krishnamurthy – LSI
Senior Director, Design Tools &
Si2 Board of Directors Chair

As we turn the leaf on another successful year of collaboration at Si2, it is time to reflect on our collective accomplishments for 2010. Si2 started off the year approving the formation of a new coalition, “OpenPDK”, with the goal of improving efficiency and interoperability for the creation of process design kits (PDKs), which are used universally across our industry. We are extremely pleased with the excitement that this new coalition has created, and we now have 15 member companies who are actively contributing to support the broad technical scope of OpenPDK. This scope includes an open process specification with reference implementation and plug-ins; enhanced, standardized symbols and parameters; CDF parameter and callback standards; PDK targeting support added to the OpenDFM standard; standard Pcell parameters; OpenAccess technology file enhancements; and a standardized SPICE socket.

2010 was also a strong year of progress for Si2’s other coalitions. The OpenAccess Coalition released support for 32nm constraints and introduced multi-threading to the reference implementation. The OAC also initiated a new Extension Steering Group to approve community-based additions to the OpenAccess schema, use models, or software that do not require changes to the base standard. The DFM Coalition released the much-anticipated OpenDFM 1.0 standard to industry, complete with a reference implementation parser, plug-in generators, and suite of test cases to verify compatibility. Not only does OpenDFM standardize leading-edge DFM parameter checks, but testing by members has found it to be as much as 20x more efficient than existing DRC formats. The Low-Power Coalition published a best-practices Interoperability Guide for design teams using both CPF and UPF-1801 formats, completed work on CPF 2.0, and released a requirements document for enhanced power modeling standards. The Open Modeling TAB delivered extensions to Liberty to enable more consistent characterization and validation of macro-cell libraries.

This was also a milestone year for membership, with Si2 expanding its representation across the supply chain. As the representative of a large fabless corporation (LSI) to Si2’s Board of Directors, I am very pleased that the Board now includes a leading foundry (GLOBALFOUNDRIES) among its elected members. The OpenAccess Coalition reached a new record high of 46 member companies in 2010, with the help of semiconductor market leaders such as Samsung, and Texas Instruments. Founding membership in the OpenPDK Coalition included all major EDA vendors.

Because of an enduring value proposition to industry, Si2 has maintained financial stability even during difficult times in our global economy. Si2 managed finances well, maintaining it’s strong 2009 fund balance and achieving a 10% increase in revenues versus 2009. This provides a solid foundation to support the tremendous amount of coalition deliverables work that has been planned for 2011.

Going into 2011, Si2’s focus will be on delivering tangible return on investment value to our membership and to the industry at large, not only with newer efforts such as OpenPDK, OpenDFM, and Open3D, but also established efforts that also require ongoing innovations in OpenAccess, low power flows, and open modeling. I am proud to serve as Chairman of this fine organization, and I call for your continued support to work alongside industry leaders to improve design flow integration and interoperability for us all. Through increased membership and participation, we can remove more barriers to reduce costs and further open market opportunity.

See the entire Si2 Member Report here.

Whither EDA in 2011?

January 6th, 2011 by Graham Bell

Dan Nenni, blogger, hosted the EDA Consortium CEO Annual CEO Forecast and Industry Vision Panel last night at the Double Tree Hotel in San Jose.  Aart de Geus from Synopsys and Charlie Huang (filling in for Lip-Bu Tan) from Cadence and Ravi Subramanian from Berkeley talked about various trends, drivers and impacts.  It was Wally Rhines from Mentor that named two possible growth numbers for 2011.   One was based on a calculation what the financial analysts say for the coming year and came in at 8%.

The second figure was based on a favorite formula that says the previous year’s R&D spend is strongly correlated to the following year’s EDA growth.  This formula delivered an exuberant  14%.

I like these numbers and I think we can expect hiring to pick up. As one exec over at a leading company mentioned to me, even marketing managers are finding jobs.

What do you think?   Do you see 8% or 14%, and will hiring pick-up?

One more thing….the Jan. 4 issue of EDA Weekly covered The Best of 2010 – EDA Weekly Magazine, Press Postings, and Careers Corner.  Check it out

Happy New Year.


CDNLive! San Jose Photo Gallery and the World Series

October 29th, 2010 by Graham Bell

I was at the Cadence CDNLive! event in San Jose on Oct. 26 at the Partner Exhibition.  There were lots of vendors and you can see the Photo Gallery of the event here.  I especially liked the happy staff at the Open Text booth.

I am also looking forward to the Baseball World Series moving to Texas.



Si2 “Much More than OpenAccess” Conference

October 21st, 2010 by Graham Bell

I attended the Reception and Product Demonstration at the Si2 OpenAccess+ Conference at the TechMart in Santa Clara, CA on Oct. 20th and spoke with Steve Schultz about all the interesting progress that is going on at Si2.

First a little background on Si2. Silicon Integration Initiative (Si2) is is a user-driven organization that addresses advanced silicon system integration issues and associated design environments for the semiconductor industry.  Si2 is focused on improving productivity and reducing cost in creating and producing integrated silicon systems.  Steve is President and CEO of Si2 which now has over 100 member companies

The four main topics areas that were covered at the conference were OpenAccess, OpenDFM, Low Power Modeling, and OpenPDKs.   In Steve’s interview, he spoke about some of the highlights and also mentioned other important developments such as 3D design.

You can listen here to the interview.

You can also see a picture gallery of the Demo and Reception area by clicking here. It includes companies such as Synopsys, SpringSoft, Calypto and Pulsic.

Go Giants!


1,000th Technical Paper Now Available

October 15th, 2010 by Graham Bell

I am very pleased  to announce that the 1,000th Technical Paper has been posted on    Our library of papers is a great resource for design teams world-wide to stay up to date on latest methods and technologies for design.

And what was the number 1000 paper?

Post-Silicon Validation Using Formal Analysis from Jasper Design Automation.

If you want to reach our audience of 75,000 unique monthly visitors and 30,000 e-news subscribers, just send your paper submission  here and select the category “Technical Papers” from the pull-down menu  or send an email to



SNPS Moves Beyond EDA to Optical Design and Analysis

October 8th, 2010 by Graham Bell

I just read the acquisition press release by Synopsys for the purchase of Optical Research Associates (ORA).  There is a lot of business activity in the area of computer displays and with LED lighting systems. You can see this in particular with the number of announcements coming out of Taiwan as its strong manufacturing operations there are trying to meet growing demand for newer, better and more efficient systems.

Is Synopsys really starting to move outside of its traditional electronic focus and embracing a new optics business model?  I think not.  ORA has a very strong consulting business and I believe that assisting customers with their electro-optical designs from IC and device through light emission and display provide the vertical alignment that will be attractive to many teams.

What are your thoughts about the requirements for electro-optical design and do you think other EDA players will also enter this part of the market?


7 New GSA Expo Videos and 3 New Event Photo Galleries

September 24th, 2010 by Graham Bell

I had the pleasure of attending the GSA Emerging Opportunities Expo & Conference in Santa Clara on Sept. 16.   I did 7 video interviews which you can see at the GSA Expo 2010 Video web-page or you can click right here:

View "40nm TSMC Multi-channel 6.5Gbps SerDes", Mahesh Tirupattur

View "Emerging Opportunities Keynote", Jodi Shelton

View "New 32nm Low Power Hi-K Metal Gate Process", Ana Hunter

View "Enhancements for Mobile Infrastructure", Art Reidel

View "New General Purpose PLL", Stephen Maneatis

Note: The keynote presented by Jodi Shelton was copied from the GSA Global Program Page.

It was a little unusual to have both the EDA Tech Forum event and the GSA Global Expo both on the same day at the Santa Clara Convention Center.  You can enjoy the photo galleries I took for the EDA Tech Forum, GSA Global Expo and the GLOBALFOUNDRIES Tech Conference events here:

EDA Tech Forum Photo Gallery (See me holding Jon Landau’s Oscar for Titanic!)

GSA Global Photo Gallery

GLOBALFOUNDRIES Tech Conference Photo Gallery



54 DAC Interviews Now Live!

July 2nd, 2010 by Graham Bell

I thought I had done lots of video interviews (44) at last year’s DAC show in San Francisco.   This year I went completely over the top and did 54!

54 EDCAfe Videos Link

One thing I noticed this year is that the interview were going longer and often lasting 5 to 6 minutes.    Everyone had something to say and we’re going to say it!

One video even has a magic trick that really works!  You will be amazed:

“Wicked Rumor, SpyGlass Physical, …and Magic!”

I also did a quick photo gallery of the different booths on the floor of the show.  You can see them at:

64 DAC Exhibit Photos

I hope you enjoy this video blog of the show and learn something that you missed at the Conference.

I wish everyone an excellent Independence Day Holiday….and for all those Canucks out there I hope your Canada Day was fun….mine was.


Three New Exhibitors You Might Miss at DAC

June 14th, 2010 by Graham Bell

I went to the DAC Web-site Exhibitor Page and counted 23 new companies exhibiting at DAC.   They span the world of design from A to Z.  We have aquintos LLC – (Model-based system design tools) to Zocalo Tech (Assertion Based Verification tools).

This leads me to conclude despite the ongoing challenges to the industry, innovators and entrepreneurs are still working hard to bring their new technologies to the design world.  Here are three new companies that are in the back-end of the design flow I think are worth taking the time to look at:

Cybereda (booth #164) is showing their new parallel SPICE tool and a new Analog Design Debug System.  They say you will get a 10X breakthrough in simulation speed and 10X faster bug killing.   I am glad to see new automation tools for analog designers.

Grid Simulation Technology (booth #1262) have two new products, NanoRAIL and SimCHECK, for tackling complex IC power  grid problems including IR voltage drop and electro-migration (EM) and the qualification of complex power network analysis results.   From what I can tell, they have a speed, accuracy and capacity breakthrough for power-net problems.

Coventor (booth #269) provides 3D MEMS simulation, analysis and design automation software for the development of micro- and nano-scale devices and systems.   Coventor has created an IC compatible MEMS + IC design flow. Its MEMS+ suite integrates with tools from Cadence and The Mathworks to enable IC designers to more efficiently incorporate MEMS into their product designs.

And finally come by the EDACafe booth #1015, and see our video studio on the floor of the DAC show.  We will be recording over 40 interviews of executives and industry leaders in front of our green screen.  I look forward to seeing you there.


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