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 The Dominion of Design
Graham Bell
Graham Bell
Graham is Sr. Director of Marketing at Real Intent. He has over 20 years experience in the design automation industry. Occasionally he writes blogs for the Dominion of Design. The views and opinions expressed in this blog are his alone and not those of his employer.

SemiCon West 2011 Video Interviews

August 29th, 2011 by Graham Bell

At SemiCon West 2011 this summer in San Francisco,  I interview a wide-range of companies from IC foundries such as  GLOBALFOUNDRIES to PCB manufacturers such as Sierra Circuits and to testing companies such as National Instruments.  And the leading EDA companies as well.

Check out all 12 interviews here.

Did you go to SemiCon West 2011?  Is the show relevant to your business?


PCI-SIG: Agilent EEsof and SiSoft Video Interviews and Exhibit Photos

June 23rd, 2011 by Graham Bell

I was at PCI-SIG in Santa Clara this week, discovering all things PCI.    Currently PCIe 3.0 runs at 8 Gbits per second, which means lots of difficulties getting signals to arrive at their destination without experiencing losses and have eye-closures and inter-symbol interference.    There is talk about at upcoming PCIe 4.0 running at 16 Gbits per second.  Now that is FAST!

I took photos of the exhibit area and also interviewed Agileen-EEsof and SiSoft technologists about their offerings.

You can click to see the videos here:

Here is the photo gallery of the exhibit area.

Caption this Photo – Win a Starbucks Gift Card!

June 9th, 2011 by Graham Bell

I was at the Denali Party  by Cadence this week in San Diego during the 2011 Design Automation Conference.   I got this photo of   Ziggy Minnelli posing with a martini.  I need a caption to go with the photo.  Please use the Comments link below to submit your entry.   The winner will receive a Starbucks Gift Card and will be announced on June 21, 2011.

Good Luck!


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Great Connections for Better Design

June 6th, 2011 by Graham Bell

I am struck at how easy it is to get used to “good enough” ways of working.  Often we fail to notice new innovations that can make our tasks easier and boost our productivity and reduce risk to success.  When asked about connecting to other design team members locally and worldwide, engineers might think of a VPN link to their office computer or the headquarters email server.  However, they would be missing the exciting developments of a whole new way of working that brings collaborative resources to bear on the design process, so that design creation, verification and integration is easier and less costly to do.

Geographically diverse design teams obviously face a number of challenges in the creation and verification of the IPs that form a functioning system-on-chip (SOC).  Design teams often grow organically and have local versions of design tools, with the related licensing and operating systems to support these tools, and means to check-in and out those designs with other teams.  Design datasets require version control of their source files, and verification sign-off steps must occur at each stage of the design process.  Questions naturally arise whether design IP has been verified using the correct application and technology libraries?

Centralized location of design files is one way to improve design management, and if the CAD licenses can be run remotely as well, then this can further benefit a structured design process and eliminate the management of CAD licenses and applications locally. Some design teams have adopted remote execution of their CAD tools from a central server, but may be forced to use expensive high-bandwidth connections to support graphical intensive applications such as IC layout or suffer with low-bandwidth connections that affect display quality.

Ideally, collaboration on a design would include shared computer desktops so graphical layouts can be reviewed and updated from diverse locations. And the connectivity solution would reduce the need for expensive high-bandwidth connections.

Connectivity solutions such as Exceed onDemand from OpenText make centralized CAD environments easy to achieve.  Their high-speed thin client graphical interface to a central location is especially architected to reduce the amount of network bandwidth to display graphical content.   Even graphically intensive 3D CAD and real-time rubber banding during layout editing is now feasible for multiple team members connected to a central location.

To simplify design control and validation as it proceeds from conception to final GDSII layout, centralized hardware and software can deliver a more stable, predictable and cost-effective design process.  Verification of IC designs takes a considerable amount of compute resources and server farms stacked with multi-CPU machines are often used to attack these problems, especially as the design proceeds closer to final tape-out.

It makes good sense to centralize these resources and gives teams robust access to them.   The freedom to launch lengthy verification runs, suspend the session from an office computer and then re-connect with that session later to monitor simulation progress, or make adjustments, allows the designers to flexibility to work from multiple locations and time zones.  Disruptions in local power or network connections do not affect the success of verification runs on a robust secure central location.

Security is also an issue with design creation and collaboration.  Centralized location of design files means synchronization of local design files is minimized and encrypted communications ensure that corporate intellectual property is preserved.  Secure and managed communications with IP suppliers and third-parties means data access can controlled as needed.

Exceed onDemand from OpenText provides the capabilities needed by SOC design teams worldwide and has been adopted by leading companies in the semiconductor industry.  Cadence Design System in EDA, Renesas in semiconductor manufacturing, and Skyworks Solutions, a fabless supplier of wireless chips have all adopted and used Exceed onDemand to made design tasks easier, boost productivity and protect the security of their design IP.  Good enough can be great with the right tool to bring our world of design together.

Embedded Systems Conf. Silicon Valley, May 2011: Sights and Sounds

May 4th, 2011 by Graham Bell

ESC SV is taking place this week at San Jose Convention Center.   On Tuesday, before I walked the convention hall, I took the time to hear a presentation by John Bruggeman, senior vice president and CMO, Cadence and Nimish Modi, senior vice president for the System and Software Realization Group at Cadence, regarding their new  System Development Suite which features two new products.  You can read more about it here.

I had my digital audio recorder switched on during the press conference.  You can hear John Bruggeman talking about App Driven Electronics and Nimish Modi giving details for the new System Development Suite and also Kevin McDermott, ARM Dir. of Marketing presenting on Cadence Co-Verification at ARM.

Below are photos I took at the press meeting, and around the conference floor.  Enjoy!


IP SOC Day Santa Clara, 2011

April 26th, 2011 by Graham Bell

Design and Reuse hosted the IP SOC Day at the Hilton Hotel in Santa Clara on April 26th.  I stopped by to catch the exhibits and take some photos.   I did get to meet Gabriele Saucier, CEO and Chair of the board.  She is tireless and continues to enjoy skiing with the grand-kids besides promoting the IP community in Europe.  Her photo is the last one in the Gallery. Enjoy!

TSMC Technology Symposium 2011 – San Jose – Interviews and Photos

April 5th, 2011 by Graham Bell

I had the pleasure of visiting the Partner Pavillion at the TSMC Technology Symposium 2011 in San Jose on April 5. While there, I took some photos which you can see in the gallery below.

I also did an audio interview with Jim McCanny of Altos Design Automation regarding their two announcements Berkeley Design Automation and Altos Design Automation Accelerate Complex I/O Characterization and Altos New 3.1 Version Speeds IP Characterization Throughput by 2-3X.  The interview can be heard here.

I also recorded an audio interview with Bernd Stamme of Kilopass regarding their announcement about the first NVM for a TSMC process: Kilopass’ TSMC 28nm HKMG Silicon Results Show Scalability of 2T Antifuse Technology.  That interview can be heard here.

Enjoy the photo gallery!


SNUG 2011 San Jose Photos

March 29th, 2011 by Graham Bell

Here are the Photos I took at the SNUG 2011 San Jose and Design Community Expo. Enjoy!

28 New Video Interviews from DVCon 2011

March 18th, 2011 by Graham Bell

EDACafe again did another round of video interiws at the DVCon 2011 Conference and Exhibition in Santa Clara on Mar. 1 and 2 up in the Press Room.   We didn’t use a green screen this time so we didn’t have the exhibitors’ booths in the background.  If you weren’t at the show or missed some of the exhibits and announcements, then you will want to check out the videos here.   I thought the interview of John Goodenough from ARM was very interesting about their use of formal verification.

I also did a photo gallery of the exhibits.  You can see the pictures here.    And as an added bonus, I took pictures at ISQED 2011 held Mar. 14-16.  You can see the ISQED pictures here.

Let me know what interviews you liked.  And for the ones you didn’t like, what question should I have asked?

And I hope your St. Patrick’s Day was green and merry.


DVCon 2011: Final Conference Program and Technical Proceedings Here

February 25th, 2011 by Graham Bell

The Design Verification Conference and Exhibition is happening Mon. Feb. 28 through Thurs. Mar. 3 at the DoubleTree Hotel, 2050 Gateway Place in San Jose, CA.

EDACafe will be doing video interviews in the Press Room – the Silicon Valley Room at the top of the stairs – and will not be in the Exhibit Hall.  There were so many new companies exhibiting we gave up our booth location so everyone could participate.

If you cannot attend the conference or just want a preview of the extensive program, then there are a number of online links you can jump to.

1.  You can see the Final Conference Program here.

2.  There are some additonal events that are not in the Final Program.

Strategies in Verification for Random Test Generation: New Techniques and Technologies: Tuesday, March 1
Donner Ballroom 6:30pm

Qualcomm Social Event: Monday, February 28
Donner Ballroom 6:00 – 8:00pm

3.  The Technical Proceedings are now online.   Below, I have expanded each of the session topics so you can jump directly to the ones that interest you.

1 UVM In Real Life
1 Easier UVM for Functional Verification by Mainstream Users
2 OVM & UVM Techniques for Terminating Tests
3 SystemVerilog FrameWorks™ Scoreboard: An Open Source Implementation Using UVM
4 First Reports from the UVM Trenches: User-friendly, Versatile and Malleable, or Just the Emperor’s New Methodology?
1P Poster Session 1
1 A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas
2 So There’s My Bug! Debugging Universal Verification Methodology (UVM) Environments
3 Interactive Command Line Debug Using UVM Sequences
4 Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis
5 Towards Provable Protocol Conformance of Serial Automotive Communication IP
2 New Frontiers In Verification
1 High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application
2 Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments
3 Parallel Computing for Functional Verification and Compute Farms: The Holy Matrimony
4 Mixed-Signal Approaches in Assertion Based Verification: New Frontiers
2P Poster Session 2
1 Linking Multiple Verification Flows Using Automatically Generated Assertions
2 Case Study: Power-aware IP and Mixed Signal Verification
3 Case Study: Low-Power Verification Success Depends on Positive Pessimism
4 Plugging the Gaps: SystemC and VHDL Functional Coverage Methodology
5 GoldMine: Automatic Assertion Generation and Coverage Closure in Design Validation
3 Mixed Signal Verification
1 An Innovative Methodology for Verifying Mixed-signal Components
2 Application of SystemC/SystemC-AMS in 3G Virtual Prototyping
3 Plan- & Metric-Driven Mixed-Signal Verification for Medical Devices
4 UVM-MS: Metrics Driven Verification of Mixed Signal Designs
4 UVM Enhancements
1 UVM Transaction Recording Enhancements
2 TLM2 in UVM
3 Advanced Testbench Configuration Using Resources
5 Acceleration Techniques
1 Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with Regard to Timing in Virtual Prototypes
2 Transaction Based Acceleration – Strong Ammunition in Any Verification Arsenal
3 Off To The Races With Your Accelerated SystemVerilog Testbench
6 Pragmatic Approaches To Verification
1 A Smart Synchronizer- Pragmatic Way to Cross Asynchronous Clock Domains
2 CompMon: Ensuring Rigorous Protocol Specification and IP Compliance
3 Addressing the Verification Challenge of SERDES-based FPGAs: The Performance/Accuracy/Efficiency Trade-off
7 Low Power Verification
1 Achieving First-Time Success with a UPF-based Low Power Verification Flow
2 Low Power Static Verification- Beyond Linting and Corruption Semantics
3 Optimizing Area and Power Using Formal Methods
8 Vertical Reuse
1 Verification Patterns in the Multicore SoC Domain
2 An Experience to Finish Code Refinement Earlier at Behavioral Level
3 Stepwise Refinement and Reuse: The Key to ESL
9 UVM Applications
1 Are Macros in OVM & UVM Evil? – A Cost-Benefit Analysis
2 Parameters and OVM – Can’t They Just Get Along?
3 From the Magician’s Hat: Developing a Multi-methodology PCIe Gen2 VIP
10 Coverage Driven Verification
1 Pay Me Now or Pay Me Later
2 Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction
3 Panning for Gold in RTL Using Transactions
11 Automated Techniques
1 Traversing the Interconnect: Automating Configurable Verification Environment Development
2 Automated Approach to Register Design and Verification of Complex SOC
3 An Automatic Visual System Performance Stress Test for TLM Designs
12 Case Studies
1 Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor Core
2 Simple & Rapid Design Verification Using SystemVerilog Testbench on Intel’s Next-Generation Microprocessor
3 Getting Rid of False Errors when Verifying LSI Designs Including Non-Determinism

I hope you find the event rewarding and educational.


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