The Dominion of Design
Graham is Sr. Director of Marketing at Real Intent. He has over 20 years experience in the design automation industry. Occasionally he writes blogs for the Dominion of Design. The views and opinions expressed in this blog are his alone and not those of his employer.
January 6th, 2012 by Graham Bell
As 2012 begins, it is time to review the stories and weekly articles that were picked by you, the EDACafe.com audience, as the most interesting and newsworthy. We have grouped them by the highest number of click-throughs or readers.
The EDA Weekly Magazine covered many different technology and business topics. The top Magazine article of 2011 was an analysis of SpringSoft, written by Russ Henke.
EDACafe has also been tracking Press Coverage throughout the year. The leading articles were a mix of customer wins, acquisition announcements and business reports, with Tanner EDA topping the list. Here are the most newsworthy corporate stories for 2011:
In the IC News category the following were the top 5 stories:
Careers Cafe authored by Mark Gilbert was also a regular feature. The following article published on Feb. 17, 2011, received an amazing 6,647 click-throughs:
The staff of Internet Business Systems and EDACafe.com thank you for your readership and wish you a prosperous 2012!
December 1st, 2011 by Graham Bell
Synopsys hosted the 24th EDA Interoperability Foum on Nov. 30 and I had the pleasure to attend the event. We listed to keynote speakers who highlighted what has changed in the last decade and what are the next challenges to be taken on. I interviewed Rich Goldman VP, Corporate Marketing and Strategic Alliances, who gave his summary of the event and the highlights from the keynote speakers. You can listen to it here.
I also took some photos which you can see below.
Yatin Trivedi also spoke with Rich for a recap of the event. You can see the video here:
November 23rd, 2011 by Graham Bell
November 9th, 2011 by Graham Bell
I was at International Conference on Computer-Aided Design (ICCAD) at the DoubleTree Hotel in San Jose this week and spoke with the General Chair, Joel Phillips about what is trending for the event. You can listen to the interview here.
I also took some photos which you can see below.
November 4th, 2011 by Graham Bell
I have a Computer Science degree from Carleton University in Ottawa, Canada which I received in 1984. Today, I am no longer doing software development or engineering work. In the area of Computer Science, there are many talented and hardworking academics who continue to advance the state of the art. One of those is Reiner Hartenstein, Professor of Computer Science, at the Technical University of Kaiserslautern on Germany.
I have never met Dr. Hartenstein, but I became acquainted with his work by chance. I am on Mentor Graphics’ email list for the various events and seminars they offer throughout the year. For some reason, the emails are addressed to Reiner Hartenstein (...Dear Reiner Hartenstein, Please come to….). I have made several attempts to have Mentor rectify the error, but to date I have not been successful.
Since Mentor had pointed out Reiner to me, I decided to do some digging with my favorite search engine and I was quickly led to Dr. Hartenstein. He is a professor at the University of Kaiserslautern, Germany, and was a visiting professor at UC Berkeley. He is a consultant and expert in EDA tools, creator of the language KARL hardware and a pioneer in VHDL and Verilog languages. He has numerous awards including being an IEEE Fellow, and has published 14 books and over 400 technical articles, and has given over 200 lectures worldwide.
Dr. Hartenstein is focused on the important area of Reconfigurable Computing (RC), typically done with FPGAs. The reason the area is important is because of the tremendous energy savings that are possible over traditional von Neumann, CPU-based computing. For some programming tasks, FPGA systems can reduce energy consumption by 3,000 times according to Dr. Hartenstein. One of the challenges for the introduction and adoption of RC is education: there is a lack of tools and methods that can be used in colleges and universities to teach effective RC.
You can learn more about Dr. Hartenstein and his research here:
What are your thoughts on alternatives to traditional computing approaches? Will we ever be effective in programming large numbers of reconfigurable datastream engines? Let me know your thoughts, below.
October 26th, 2011 by Graham Bell
Oct. 25 at the Santa Clara Convention Center was ARM Techcon 2011 – Chip Design Day. While walking the Exhibit Hall, I met Lori Kate Smith, Sr. Manager Community Programs at ARM. She introduced me to James Bruce, Lead Mobile Strategist at ARM who see the vision for the next 3 to 5 years in the Mobile space. James gave a very interesting interview which can be heard here.
I also stopped by the Atrenta booth and spoke with Mike Gianfagna, V.P. of Marketing who talked about Early PPA analysis on AMBA-based designs. We talked about how early what-if analysis of performance, power and area on different candidate SOC architecture implementations. You can hear the interview with Mike here.
Besides the interviews, I also took photos of the exhibits and visitors to the event. You can see the photo gallery below.
September 29th, 2011 by Graham Bell
I had the pleasure of attending the Open House for Jasper Design Automation’s new HQ in Mountain View on Thursday, September 22. Kathryn Kranen, CEO and her staff put on a great event. I mixed and mingled with semiconductor and EDA industry movers and shakers, tried my luck at the casino stations and enjoyed good food and drink. There was a prize raffle at the end where Lady Luck shone on me and I won some cool items.
Kathryn graciously took some time to spend a few minutes with me and give us an update on new hiring and business at Jasper. You can listen to the audio interview here.
Finally I took some pictures (below) at the event. You can see we had a good time.
September 23rd, 2011 by Graham Bell
The 1st Nanometer Circuit Verification Forum took place on Thursday, Sept. 22 at the TechMart in Santa Clara. Hosted by Berkeley Design Automation, the forum presented user experiences with verification of new nm high-performance analog/mixed-signal designs. The keynote was by Jim Hogan and over 100 were in attendance. BDA’s Analog Fast Spice product is making a big impact for design teams who need answers faster but cannot sacrifice accuracy.
I had the pleasure of speaking with Ravi Subramanian, CEO of Berkeley who gave his summary of the event in an audio interview (click here).
One of the most often heard questions at the event was “Will there be another Forum in the future”? Because of the very positive response by the attendees to the forum’s sharing of real experiences, the answer is a resounding ‘yes’. And there may be Forum’s held in other locations world-wide.
At the end of the forum was a reception, where I took photos. You can see the gallery below
September 16th, 2011 by Graham Bell
I received this issue of the Linley Wire and thought you would be interested in seeing the analysis of recent networking developments.
Linley Wire, Volume 11, Issue 9
September 16, 2011
Independent Analysis of the Networking-Silicon Industry
Editor: Bob Wheeler
In This Issue:
-Now Available: A Guide to High-Speed Embedded Processors
To read these articles on-line, click here
Now Available: A Guide to High-Speed Embedded Processors
The Linley Group’s new report “A Guide to High-Speed Embedded Processors” is now available for immediate delivery. This completely revised report provides extensive coverage of high-end embedded processors with 317 pages of information on AppliedMicro, AMD, Broadcom, Cavium, Freescale, Intel, LSI, Marvell, NetLogic, STMicroelectronics, Texas Instruments, Tilera, Ubicom, Via Technologies, and Xilinx. For more details on this report, access http://www.linleygroup.com/report_detail.php?num=20
This week, Broadcom announced that it will acquire NetLogic Microsystems for $3.7 billion. Broadcom’s largest acquisition, NetLogic will become part of the Infrastructure and Networking Group (ING) under Rajiv Ramaswami. ING rang up $1.6 billion in revenue last year, mainly on shipments of Ethernet chips, contributing about a quarter of the company’s total revenue. NetLogic adds a business that had revenue of $382 million last year and a staff of 645 employees. The NetLogic product lines that contributed the bulk of last year’s business were embedded processors and KBPs (Knowledge Based Processors). NetLogic also has a 10G Ethernet PHY product line, but this line generated significantly less revenue and was not consequential to the acquisition.
For NetLogic, consolidation at this princely sum is a wonderful exit to a charmed life. In the highly competitive search coprocessor market, NetLogic evolved from a startup to the dominant supplier while one-by-one its competitors folded operations. The company expanded its target market by acquiring RMI for $183 million, and that business grew as a result of excellent leadership and favorable market conditions. Looking forward, NetLogic faced a more challenging environment. Cavium is entering the search coprocessor market with an innovative product that has a strong potential to win market share from NetLogic. Additionally, NetLogic’s execution on its next-generation XLP processor has been weak, which had the potential to impact future growth.
As a part of Broadcom, the KBP business is more defendable, and the processor business should benefit from Broadcom’s considerable engineering and sales resources to improve execution and win market share. For Broadcom, this deal provides a family of multicore MIPS-compatible processors. The XLP processor is popular in networking and communications equipment, a market where Broadcom is currently the leading supplier of Ethernet chips. Broadcom will be able to expand its networking target market by bundling Ethernet chips with data-plane and control-plane processors. Additionally, NetLogic gives Broadcom an opportunity to become a major player in the larger embedded processor market—where the company currently has only a small share generated from legacy products.
With this acquisition, Broadcom also gets wireless base station DFE (digital front-end) chips, which came to NetLogic through its Optichron acquisition earlier this year. In the last year, ING has targeted base stations and related technologies through internal Carrier Ethernet switches and acquisitions. In 4Q10, it acquired Percello, which was developing femtocell processors. Earlier this year it acquired Provigent, which was developing microwave backhaul components. While Broadcom has built a portfolio of mobile infrastructure components, the company has yet to articulate a platform strategy that cohesively combines them all.
NetLogic Previews 28nm XLP
One week before the Broadcom acquisition was announced, NetLogic Microsystems announced its plans to move its XLP processor into 28nm technology, with the first products sampling in 1Q12, according to the company. The next-generation manufacturing process will enable the company to increase the number of CPUs from 8 in the current 40nm XLP to a maximum of 20 in the forthcoming XLP II family. NetLogic has set a clock-speed target of 2.5GHz for the 28nm parts, 25% faster than the target for the current XLP. With the increase in both clock speed and core count, the XLP II is rated at 100Gbps of packet-processing throughput; the company did not specify the type of processing that can be performed at this rate.
Like the XLP, the new processors will support multisocket cache-coherent implementations using proprietary chip-to-chip interfaces called ICI. The XLP II will add a fourth ICI port, enabling designs with eight processor chips and 160 CPUs working together in a single coherent memory model. This coherent model simplifies programming, eliminating the need for software pipelining or other forms of partitioning. No competing processor vendor provides scalability to this level of performance.
In most other ways, the new processors will be similar to the existing XLP, which features a four-way superscalar CPU with simultaneous multithreading and a variety of accelerators, including encryption, reg-ex, compression, de-duplication, TCP, and RAID engines. To support the additional CPUs, the XLP II will increase the size of the on-chip caches and support the latest DDR3 memory speeds. The company did not disclose details such as power dissipation or pricing for the next-generation products.
Unlike most processor vendors, NetLogic has extensive experience with 28nm technology. The company has already developed multiple products, including 10G Ethernet PHYs and search coprocessors, in TSMC’s 28nm HP technology. This experience should ease the development of the XLP II, which we assume uses the same process. Freescale has also announced plans to sample its first 28nm processor, the T4240, in 1Q12. Thus, the two companies are in a horserace to deliver the first 28nm multicore processor.
The XLP II offers impressive specifications that should keep it at the forefront of performance. By extending its unique multisocket scalability, the new processor will be particularly well suited to extremely demanding applications. A more complete analysis, however, must await a full disclosure of the product’s details.
NetLogic will disclose additional details of the XLP II architecture at the Linley Tech Processor Conference on October 5–6. For more information on this event, access http://www.linleygroup.com/events/event.php?num=10
Cavium Enters Search Coprocessor Market
In August, Cavium announced its upcoming family of search coprocessors. The products include the Neuron Search and the Neuronmax Search lines of coprocessors. The former is a standalone search coprocessor that integrates all required memory, while the latter uses a combination of on-chip and external memory. The primary difference between these components is the addition of a DDR3 controller in Neuronmax Search.
Scheduled to sample in 1Q12, these coprocessors perform Layer 2 through Layer 4 lookups for networking equipment in the enterprise and service provider markets. Specifically, each device can perform LPM (longest prefix match) and ACL-rule lookups. Instead of using a TCAM-based architecture, Cavium has developed proprietary technology to perform LPM and ACL lookups. The company claims Neuron Search provides 4× the capacity of a 40Mb TCAM at half the power, giving it a tremendous advantage. Neuronmax Search uses external memory to support up to 20 times the capacity of Neuron Search.
The Neuron Search family interfaces to a network processor using Interlaken LA or a parallel bus. With Interlaken, Neuron Search supports the latest NPUs, while the parallel interface supports legacy NPUs. Cavium plans to offer family members at different performance levels, ranging from 100 million searches per second to 1.6 billion searches per second with guaranteed latency.
Cavium enters the search coprocessor market at the beginning of a new growth spurt, which is driven by the move from IPv4 to IPv6 combined with greater port rates. By guaranteeing latency, Cavium has addressed the traditional issue associated with algorithmic solutions. At the same time, Neuron/Neuronmax Search are set to take the lead in capacity per watt. With its power and density advantages, Neuron/Neuronmax Search are well positioned to win designs against traditional TCAM-based search coprocessors.
Additional coverage of search coprocessors appears in our report “A Guide to Network Processors”.
Access our web site for more details: http://www.linleygroup.com/report_detail.php?num=13
Cortina Processor Opens Gateways
Cortina has developed a new gateway processor featuring a dual-core 400–800MHz ARM Cortex-A9. Accelerators enable 2Gbps of data-plane performance and relieve the CPUs of network-processing functions, such as network address translation (NAT), encryption, packet prioritization, upper-level MAC functions for Wi-Fi, and TCP operations including segmentation and reassembly. CPU cycles are at a premium because next-generation gateways must handle data at gigabit rates while performing services such as dishing out video to TVs and to thin-client set-top-boxes. There’s also talk of running Java applications, and even Android, on gateways. Such applications leave little time for CPUs to chase packets.
Typical of gateway processors, the CS7542 features three Gigabit Ethernet ports. In a standard configuration, one port connects to a broadband modem, another to a home-networking (e.g., Moca, HPNA, or HomePlug) chip, and the third to an Ethernet switch to fan out to other LAN ports. Three multiplexed PCI Express/SATA ports provide connections to peripherals such as Wi-Fi transceivers and disk drives. An additional unmultiplexed SATA interface brings the total of possible direct-attached drives to four, enabling construction of a four-bay home-storage (NAS) system without use of external port multipliers or controllers.
An unusual feature is the CS7542’s six MPEG Transport Stream (MPEG-TS) interfaces, which accept data from satellite, cable, and terrestrial TV receivers. The CS7542 can, for example, wrap these streams in a copy-protection layer and beam them to networked devices over its Ethernet ports. For audio output, the processor has a pair of PCM interfaces, enabling the processor to adapt VoIP to analog telephones. Ports for I2S and SPDIF provide output for high-quality audio. For displaying management information, the processor connects directly to LCD panels. High-quality video requires an external PCIe-based video decoder.
The market for PON gateways is much smaller than for DSL gateways, making it difficult for vendors of PON gateway processors to establish a profitable business. None of these suppliers has created a sustainable franchise; developing a gateway processor is clearly easier than selling one. As in DSL, broadband integration is inevitable, and Cortina is well positioned to combine its EPON controller into its gateway processor in the future. In the meantime, the CS7542 validates Cortina’s processor technology and offers some unique features that should help it win designs.
Processor Conference October 5-6 in San Jose
Twenty of the most influential suppliers of processors for networking and communications will present their newest technologies at the 2011 Linley Tech Processor Conference. Click here to see a detailed program and to register for this not to be missed event.
Keynote speakers include Linley Gwennap, Principal Analyst for The Linley
This two-day single-track event also has sessions dedicated to:
About Linley Wire
Linley Wire is a free electronic newsletter published by The Linley Group, a technology analysis and strategic consulting firm. Linley Wire will present our analysis of recent news on semiconductors for networking and communications. Articles are posted weekly to our web site and sent monthly via email. To access the web content directly, visit our web site.
Linley Wire is not affiliated with any outside vendors. We do not rent or sell our mailing list; it is used only to send you the newsletter and information on our events.
We encourage you to forward this newsletter to colleagues who may benefit from receiving this information. They may subscribe by visiting our web site.
Copyright 2011, The Linley Group
August 31st, 2011 by Graham Bell
I had the pleasure of attending the GLOBALFOUNDRIES Global Technology Conference at the Santa Clara convention center on Aug. 30. There were partnership and EDA design flow announcements from the major vendors for the new 20nm process. By successfully taping out a test chip using flows from leading EDA vendors Cadence Design Systems, Magma Design Automation, Mentor Graphics Corporation, and Synopsys Inc., GLOBALFOUNDRIES demonstrated that it is ready for customers to begin evaluating their 20nm designs.
There was also a GLOBALSOLUTIONS ecosystem pavilion where over 40 different partners talked about their solutions. The exhibits looked great and were easy to get around. I took some photos of the event and you can see them below.