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 The Dominion of Design
Graham Bell
Graham Bell
Graham is Sr. Director of Marketing at Real Intent. He has over 20 years experience in the design automation industry. Occasionally he writes blogs for the Dominion of Design. The views and opinions expressed in this blog are his alone and not those of his employer.

CDNLive! 2012 Silicon Valley – Two Keynotes, an Interview and Photos

 
March 15th, 2012 by Graham Bell

Cadence held their CDNLive! 2012 Silicon Valley event at the DoubleTree Hotel in San Jose, CA on Mar. 13 and 14.   I had the pleasure of hearing two keynotes by Rick Cassidy, President of TSMC North America and Tom Lantzsch, Exec VP of  Corporate Development at ARM.  Both addressed the growing challenges and opportunities for the next generation of low-power smart devices that will be coming in the future but from two different angles:

“CDNLive Keynote: The Silicon Century and the Future Ahead”, Rick Cassidy, Pres. TSMC N.A.

“CDNLive Keynote: The Future of Smarter Systems, Apps, Internet of Things”, Tom Lantzsch, Exec. V.P. Corp. Development, ARM

I also spoke with Rod Simon from OpenText who was exhibiting at the Design Expo. He was presenting their secure high-speed remote connectivity product and a new MS-Outlook plug-in for huge file transfers that is secure and trackable.  Follow this link to hear this 4 min.  interview:

“Exceed onDemand and New Managed File Transfer”, Rod SimonOpenText Connectivity Solutions Group

I also took photos at the Design Expo.  Enjoy! Read the rest of CDNLive! 2012 Silicon Valley – Two Keynotes, an Interview and Photos

Design and Verification Conf. 2012 – Videos, Pictures, and I predict the future

 
March 12th, 2012 by Graham Bell

I was at DVCon 2012 in San Jose, CA, and did over 25 video interviews at the event with different exhibitors, analysts such as Gary Smith, and industry colleagues such as Mark Gilbert of EDA Careers and Ali Iranmanesh of the International Society for Quality Electronic Design.   I also was on the ‘receiving end’ of some questions, when Ed Lee of LeePR graciously took the time to ask me about the state and future of EDA, EDA PR and EDACafe.com.  It was a great event, with a lot of traffic, new exhibitors, and growing attendance.

You can see all of the DVCon 2012 videos here.

Also at DVCon 2102,  I took photos of the booths and exhibits, which you can see below. Read the rest of Design and Verification Conf. 2012 – Videos, Pictures, and I predict the future

Interview with Herman Chu, General Chair, SEMI-THERM Conference, March 18-22, San Jose, CA

 
March 8th, 2012 by Graham Bell

I had the pleasure of speaking with Herman Chu, General Chair, SEMI-THERM Conference that is taking place at the DoubleTree Hotel,  March 18-22, in San Jose, CA.   Herman talked about the inflection point we are undergoing right now with thermal demands of electronic systems, and how the SEMI-THERM conference will address those challenges.

You can hear the interview with Herman Chu here.

EDAC’s CEO Forecast Panel

 
March 8th, 2012 by Graham Bell

This DAC blog is from March 2, 2012 by Paul McLellan

 

This year’s CEO forecast panel was held at Silicon Valley Bank. Bankers live better than verification engineers, as if you didn’t know, based on the quality of the wine they were serving!

This year the panellists were Ed Cheng from Gradient, Lip-Bu, Aart and Wally (and if you don’t know who they are you haven’t been paying attention) and Simon Segars of ARM (not their CEO, of course). Ed Sperling moderated. Somebody had managed to dig up the fact that at the start of his career he’d been a crime reporter, so that made sure that we only got truthful answers all evening!

Read More

Addressing the Design Power Gap and ANSYS / Apache Product Roadmap and Integration

 
March 5th, 2012 by Graham Bell

At DesignCon 2012, I had the pleasure of speaking with Vic Kulkarni, Senior Vice President & General Manager of Apache,  about the issues surrounding the Power Gap in product design.  I also spoke separately with Larry Williams from ANSYS and Aveek Sarkar from Apache Design, Inc. which was acquired by ANSYS in Aug. 2011.

The acquisition of Apache complements ANSYS’ software solutions by bringing together best-in-class products that drive ANSYS’ system vision for integrated circuits, electronic packages and printed circuit boards. The complementary combination is expected to accelerate development and delivery of new and innovative products to the marketplace while lowering design and engineering costs for customers.

To understand the issues around the Design Power Gap and how Power Artist from Apache can help  listen to the interview below.

Read the rest of Addressing the Design Power Gap and ANSYS / Apache Product Roadmap and Integration

Video and Tech Paper: Simulating Large Systems with Thousands of Serial Links

 
February 29th, 2012 by Graham Bell

I spoke with Todd Westerhoff of SiSoft about their new Virtual Prototype Analysis that can  simulate large systems with thousands of serial links at DesignCon 2012.  You can see the video interview here and below is a short description and link to a technical paper that described the analysis of such a large system.

While not long ago systems had only several serial links, it’s now becoming common for systems to include hundreds – and even thousands – of such links. This paper describes the development and analysis of a large system with thousands of serial links. Due to the system’s size and complexity, the design team invested in a multi-year effort to build and qualify a virtual environment capable of both verifying connectivity and simulating any and all of the channels. Problematic channels with incomplete system-level connections, poor eye openings, or high BER are quickly identified. Performance limiters such as inherent discontinuities (and their associated resonances), and Tx/Rx equalization imbalance are found and examined in detail. The virtual system is also used to guide design choices such as layer stacking, via construction, back-drilling, and trace/connector impedances. Processes to optimize and select equalization choices are also described.

Click here to read Simulating Large Systems with Thousands of Serial Links.

Click here for more information on Virtual Prototype Analysis.

Reinventing the EDACafe Weekly

 
February 23rd, 2012 by Graham Bell

Welcome to the new “EDACafe Weekly.”   Every Monday you will be receiving a summary of the previous weeks EDACafe blog postings, including our featured writer Peggy Aycinena.   There will be postings from my blogs: Video Roundup, The Dominion of Design and IP Showcase, that cover the various facets of creating new electronic designs.  And of course, all the other blog contributors from the past week.

We look forward to hearing your comments about the new format….and let me know if you would like to start a blog on EDACafe.

+Graham

Panel on HW/SW Co-design from the Software Perspective, Mon. Feb. 27

 
February 21st, 2012 by Graham Bell
EDA companies often address hardware/software co-design from a hardware point of view. ie, how can software developers run their software on this representation of a chip that was designed on our tools. This viewpoint often overlooks the real concerns of software developers. Today, since software is the fastest growing and the largest engineering content of a SoC/ASIC design, it is time for the EDA industry to understand the needs and concerns of the software industry. This panel attempts to address these needs and concerns. 

The panel is organized by Paul McLellan, an EDA industry: guru, veteran, analyst and author. He has extensive experience in IC design, software development and system virtualization . In particular he was VP marketing at VaST (since acquired by Synopsys) and Virtutech (since acquired by Wind River/Intel). The panelists include software engineering managers who are responsible for SoC/ASIC software development at major corporations. After the panelists discuss their issues there is a 30 minutes audience questions and answers session.

Moderator:
• Paul McLellan, EDA Industry Analyst and Author, EDA Graffiti
Organizer:
• EDAC Emerging Companies Committee
Panelists:
• Michael James, Senior Staff Engineer, Lockheed-Martin Space Systems Company
• Atul Kwatra, Principal Engineer, Intel corporation
• Bill Neifert, Chief Technology Officer, Carbon Design Systems
• Don Williams, Head of Core Technology, Skype
Date: Monday, February 27, 2012
Time: 6:30 PM to 9:00 PM.
Location: DoubleTree Hotel, 2050 Gateway Place, San Jose, CA 95110 (Co-located with DVCon) 

 

Register Now

Upcoming EDA Consortium Annual CEO Forecast and Industry Vision, Feb. 29 …And See What They Said in 2011

 
February 17th, 2012 by Graham Bell

Click Here to see what the CEO and Executives said in 2011.  Were they right?

DesignCon 2012 Video Interviews and Photo Gallery

 
February 10th, 2012 by Graham Bell

I was doing video interviews at DesignCon 2012 in Santa Clara last week.   The event was busy with lots of attendees and presentations.  You can enjoy over 20 interviews covering all the advancements in high-frequency IC, board and system design at the following page:

DesignCon 2012 Video Interviews

I also took the time to walk the show floor and take photos of various booths and attendees at the event.  You can enjoy the gallery below.

Happy Valentines Day!

+Graham

Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL
DAC2018



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