Sanjay Gangal Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999.
ASQED 2012 was held on July 10-11 at Penang, Malaysia.
The 4th Asia Symposium on Quality Electronic Design (ASQED 2012) was the fourth event organized by the International Society for Quality Electronic Design with technical sponsorship from several IEEE Societies. This event was sponsored and managed by SHRDC. ASQED emphasizes innovations and the latest developments in System and IC Design, MEMS & NEMS, Semiconductor Technology & Manufacturing, IC Packaging & PCB Technology, Test, and Bio & Nano Electronics.
ASQED Microelectronic Olympiad winner received the award from Rich Goldman of Synopsys. From left: Prof. Amin Bermak, Dr. Ali Iranmanesh, Mr. Rich Goldman, Mr. Reza Asadpour, Prof. Osseiran.
Before I step on stage for a performance, I look at the crowd and say, “Lord, please don’t let me screw this up.” But it is the effort before this performance that really leads to this moment. First we have a casting process, where we try to find the best actor to play the lead, then the understudy, then the extras and technical team etc. This is usually done by a director, someone who has excelled at acting before, and develops the entire vision. Then we memorize our lines, this is the most mind-numbing and difficult part, so to prevent mental break downs, we divide the script up into smaller parts. We start with a few simple lines, then progressively add more lines and difficulty of memorization. Then we block the entire play, see what goes where, and perform it. Next, we have dress rehearsals, we get comfortable performing in our costumes and make sure things go off without a hitch. Now after all of this, we present it to the audience and hope that we don’t get pelted with tomatoes. After we perform, we wait for the audience to react, if they respond with cheers, we repeat the act the same way the next night with minor adjustments, if we are hurt and killed with articles of food, we then see what to improve and make changes for the next show.
The DAC frenzy has begun. We at Jasper are excited to be going to DAC and showing the industry the latest in our leading Jasper formal technology.
We recently introduced our JasperGold Apps that help customers achieve substantial productivity gains in design and verification through individual Apps within a shared interactive environment that fit into existing verification flows. The JasperGold Apps helps solve engineers’ toughest problems, addressing an array of design and verification functionality issues throughout the flow, such as:
End-to-end property verification,
Unexpected X detection and debugging,
Automated assertion generation,
Identification of coverage holes,
Design trade-off analysis,
Absence of deadlock,
And many more.
You can see the JasperGold Apps in action in our booth.
It seems that HP has invested in its hardware division big time with several unveilings this week, including notebook PCs, the HP Photosmart 5520 e-All-in-One printer, Ultrabook and Sleekbook offerings as well as for businesses, the HP t410 All-in-One (AiO) Smart Zero Client.
HP Pavilion notebook PCs include enhanced features and reflect the company’s new HP Mosaic design approach.
Calypto has just published a new report on trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey. The survey was executed in late 2011 and had 744 SoC, IC, and FPGA design professionals respond; this report will analyze the survey results and identify relevant year-to-year trends.
By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65 nm and beyond.
The topics covered in this report are:
Survey methodology and demographics
Top methods used to reduce power
Percent of engineering time spent meeting power specifications
Top criteria for selecting RTL power optimization tools
Process nodes where RTL power optimization becomes important
Plans to implement power optimization tools in 2012
In a design ecosystem increasingly influenced by software and systems development, massive verification demands, and the boundaries of physics, engineers have a wonderful new set of problems to solve! Yet the principles they will use to innovate their way to exciting solutions and products remain as fundamental and universal as the reality of the Golden Ratio itself. With the aid of some of these principles, Aart talks about what new strategies and methodologies semiconductor players will need to achieve the critical mass necessary to craft productive and creative solutions within a design ecosystem complexity that surpasses anything seen yet in human history.
Click on the graphic to view the video.
Dr. Aart de Geus
CEO & Chairman of the Board
The importance behind secure and fast file transfer plays a huge factor as it relates to the productivity within an engineering design workflow. Design engineers and semiconductor companies need to boost team collaboration through fast and secure content sharing around the globe to get their designs finalized and onto the chip manufacturer for creation.
Learn how to optimize the engineering design workflow and send your LARGE files faster with this new whitepaper:
Cadence Press just introduced a new title on Advanced Verification Topics by Bishnupriya Bhattacharya and contributors. Here is a small quote from what Adam Sherer, Cadence Product Marketing Director, said in the Preface to the book:
Consumers may perceive that “it’s a digital world,” but these advanced verification topics speak to the magic that goes on under the hood of every SoC. As verification engineering managers and team leaders, we know that MDV, multi-language VIP, low-power, mixed-signal, and acceleration topics are converging at 20 nm and beyond; but we don’t want to create whole new methodologies for each one. The authors of this book realized this, and selected the Accellera UVM standard as the common base from which to offer solutions that leverage reuse and raise team-level productivity. That’s why we have written this book—not only for verification engineers familiar with the UVM and the benefits it brings to digital verification, but also for verification engineers who need to tackle these advanced tasks. Though the solutions in this book are not standardized, most of them are available through open-source code. For all of you, the material in this Advanced Verification Topics book is provided as a means to stay productive and profitable in the face of growing verification complexity.
EDACafe has exclusive previews of the text by clicking on the links below.