The Dominion of Design

Sanjay Gangal
Sanjay Gangal
Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999.

“Novel New Vertically-Oriented, Antifuse Non-Volatile Memory Bit Cell” by Harry Luan, CTO of Kilopass Technology

 
October 22nd, 2012 by Sanjay Gangal

Article source: Kilopass Technology

Harry Luan, chief technology officer at Kilopass Technology Inc., a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP) presenting “Novel New Vertically-Oriented, Antifuse Non-Volatile Memory Bit Cell” at MemCon 2012 on Tuesday, September 18, at 2:15 p.m. at the Santa Clara Convention Center, Santa Clara, Calif.

The new embedded VCM (Vertical Cross-point Memory) NVM IP bit cell quadruples the density of today’s anti-fuse NVM IP bit cell. The VCM bit cell will make possible program storage where today’s embedded non-volatile memory (eNVM) technology is cost-prohibitive or unavailable at capacities of 4Mb to 32Mb. It will also enable a higher level of performance more similar to SRAM compared to existing slower eNVM technologies or external flash or EEPROM chips.

Read the rest of this entry »

‘Invisibility’ could be a key to better electronics

 
October 11th, 2012 by Sanjay Gangal

Author: David Chandler, MIT News Office

MIT team applies technology developed for visual ‘cloaking’ to enable more efficient transfer of electrons.

A new approach that allows objects to become “invisible” has now been applied to an entirely different area: letting particles “hide” from passing electrons, which could lead to more efficient thermoelectric devices and new kinds of electronics.

The concept — developed by MIT graduate student Bolin Liao, former postdoc Mona Zebarjadi (now an assistant professor at Rutgers University), research scientist Keivan Esfarjani, and mechanical engineering professor Gang Chen — is described in a paper in the journal Physical Review Letters.

Diagram shows the 'probability flux' of electrons, a representation of the paths of electrons as they pass through an 'invisible' nanoparticle. While the paths are bent as they enter the particle, they are subsequently bent back so that they re-emerge from the other side on the same trajectory they started with — just as if the particle wasn't there. - Image courtesy Bolin Liao et al.

Normally, electrons travel through a material in a way that is similar to the motion of electromagnetic waves, including light; their behavior can be described by wave equations. That led the MIT researchers to the idea of harnessing the cloaking mechanisms developed to shield objects from view — but applying it to the movement of electrons, which is key to electronic and thermoelectric devices.

Read the rest of this entry »

The Measure of Nanometer Silicon Success

 
September 24th, 2012 by Graham Bell

I was speaking with experts at Mentor about the latest developments in back-end physical verification (PV) and design-for-manufacturing (DFM).  It prompted me to take a look at what has changed and what will be essential going forward. Here is what I see for this critical area for IC implementation.

First, we have passed the 28nm barrier and are already looking to a new generation of design. Leading-edge design starts are now at 20nm and we will see production silicon for that node by early 2013.  However, in a new research brief, “Driving first-time silicon success across the IC ecosystem,” by Dr. Handel Jones, semiconductor analyst at IBS, the total number of design starts is not growing.  While System integrators such as Samsung and Apple, are furiously growing their mobile businesses, the ability to integrate ever-larger collections of IP in their SOCs means they do not need to include more ICs in their phones to expand the features of their products.  It is also true that 20nm designs have a much higher NRE than previous generations.  Naturally, this economic incentive will keep some design starts at the 28nm and larger nodes.

Read the rest of this entry »

ASQED 2012 in Malaysia a huge success!

 
July 31st, 2012 by Sanjay Gangal

Article source: ASQED

ASQED 2012 was held on July 10-11 at Penang, Malaysia.

The 4th Asia Symposium on Quality Electronic Design (ASQED 2012) was the fourth event organized by the International Society for Quality Electronic Design with technical sponsorship from several IEEE Societies. This event was sponsored and managed by SHRDC. ASQED emphasizes innovations and the latest developments in System and IC Design, MEMS & NEMS, Semiconductor Technology & Manufacturing, IC Packaging & PCB Technology, Test, and Bio & Nano Electronics.

 

ASQED Microelectronic Olympiad winner received the award from Rich Goldman of Synopsys. From left: Prof. Amin Bermak, Dr. Ali Iranmanesh, Mr. Rich Goldman, Mr. Reza Asadpour, Prof. Osseiran.

Read the rest of this entry »

The World of Drama and the Verification Engineer – A High Schooler’s Perspective

 
June 28th, 2012 by Shachi Nandan Kakkar

Before I step on stage for a performance, I look at the crowd and say, “Lord, please don’t let me screw this up.” But it is the effort before this performance that really leads to this moment. First we have a casting process, where we try to find the best actor to play the lead, then the understudy, then the extras and technical team etc. This is usually done by a director, someone who has excelled at acting before, and develops the entire vision. Then we memorize our lines, this is the most mind-numbing and difficult part, so to prevent mental break downs, we divide the script up into smaller parts. We start with a few simple lines, then progressively add more lines and difficulty of memorization. Then we block the entire play, see what goes where, and perform it. Next, we have dress rehearsals, we get comfortable performing in our costumes and make sure things go off without a hitch. Now after all of this, we present it to the audience and hope that we don’t get pelted with tomatoes. After we perform, we wait for the audience to react, if they respond with cheers, we repeat the act the same way the next night with minor adjustments, if we are hurt and killed with articles of food, we then see what to improve and make changes for the next show.

Read the rest of this entry »

Upgrading Your Verification with Jasper!

 
May 23rd, 2012 by Rob van Blommestein

The DAC frenzy has begun.  We at Jasper are excited to be going to DAC and showing the industry the latest in our leading Jasper formal technology.

We recently introduced our JasperGold Apps that help customers achieve substantial productivity gains in design and verification through individual Apps within a shared interactive environment that fit into existing verification flows.  The JasperGold Apps helps solve engineers’ toughest problems, addressing an array of design and verification functionality issues throughout the flow, such as:

  • End-to-end property verification,
  • Unexpected X detection and debugging,
  • Chip-level connectivity,
  • Automated assertion generation,
  • Identification of coverage holes,
  • Design trade-off analysis,
  • Absence of deadlock,
  • Cache coherency,
  • And many more.

You can see the JasperGold Apps in action in our booth.

Read the rest of this entry »

Sizzling new offerings from HP

 
May 10th, 2012 by Susan Smith

It seems that HP has invested in its hardware division big time with several unveilings this week, including notebook PCs, the HP Photosmart 5520 e-All-in-One printer, Ultrabook and Sleekbook offerings as well as for businesses, the HP t410 All-in-One (AiO) Smart Zero Client.

HP Pavilion notebook PCs include enhanced features and reflect the company’s new HP Mosaic design approach.

Read the rest of this entry »

New Low Power RTL Analysis and Optimization Report

 
April 27th, 2012 by Graham Bell

Calypto has just published a new report on trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey. The survey was executed in late 2011 and had 744 SoC, IC, and FPGA design professionals respond; this report will analyze the survey results and identify relevant year-to-year trends.

By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65 nm and beyond.

The topics covered in this report are:

  1. Survey methodology and demographics
  2. Top methods used to reduce power
  3. Percent of engineering time spent meeting power specifications
  4. Top criteria for selecting RTL power optimization tools
  5. Process nodes where RTL power optimization becomes important
  6. Plans to implement power optimization tools in 2012
  7. Conclusion

Click here to see the Low Power RTL Report.

 

Aart’s SNUG Silicon Valley Keynote – Critical Mass, Systemic Complexity and Innovation: Catalysts for Designing Change

 
April 26th, 2012 by Graham Bell

In a design ecosystem increasingly influenced by software and systems development, massive verification demands, and the boundaries of physics, engineers have a wonderful new set of problems to solve! Yet the principles they will use to innovate their way to exciting solutions and products remain as fundamental and universal as the reality of the Golden Ratio itself. With the aid of some of these principles, Aart talks about what new strategies and methodologies semiconductor players will need to achieve the critical mass necessary to craft productive and creative solutions within a design ecosystem complexity that surpasses anything seen yet in human history.

Click on the graphic to view the video.

SNUG 2012

Aart de Geus

Dr. Aart de Geus
CEO & Chairman of the Board
Synopsys

SNUG 2012 Keynote - Aart de Geus - Critical Mass, Systemic Complexity and Innovation: Catalysts for Designing Change

DVCon 2012 Technical Presentations Now Available

 
April 20th, 2012 by Graham Bell

The technical paper presentation from the Verification conference DVCon 2012 are now available online at the DVCon web-site.  You can them listed here below.

Use the BACKSPACE key to return to the main menu after drilling down into any of the sessions.

Pop-ups must be enabled to view any of the papers or slides.

CAD/SW Engineer
Technical Writer (synthesis, place and route)



Click here for Internet Business Systems © 2014 Internet Business Systems, Inc.
595 Millich Dr., Suite 210, Campbell, CA 95008
+1 (408) 850-9202 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and ResumesEDACafe - Electronic Design AutomationGISCafe - Geographical Information Services	MCADCafe - Mechanical Design and EngineeringShareCG  - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy