Median income for electrotechnology and information technology professionals jumped by more than 4 percent in 2014, the largest increase in the past five years, according to the 2015 IEEE-USASalary & Benefits Survey.
Median incomes from primary sources — salary, commissions, bonuses and net self-employment income — for U.S. IEEE members working full-time in their primary area of technical competence (job specialty) rose from $124,700 in the 2013 tax year to $130,000 in 2014.
The 4.25 percent increase comes a year after median income rose by its small percentage over the past five years, .56 percent.
The results are based on survey responses from 10,215 people. Here are median incomes since 2009:
Those employed in communications technology once again enjoyed the highest median earnings ($150,000), followed by circuits and devices ($143,008) and signals and applications ($141,062).
Design engineers are increasingly spending their time on verification. Research suggests that it is now more than 50% of their time and, according to Harry Foster of Mentor Graphics in his lighter moments, if we continue the current linear trend then it will reach 100% by 2030! So why is verification so demanding? It seems that IP reuse has enabled designers to create larger, more complex designs to keep pace with our manufacturing capability but our verification productivity has not kept pace.
Looking to tools for productivity gains, EDAC (the EDA Consortium) reported that the overall EDA verification market grew by 38% from 2010 to 2012 with emulation up by 94%. But, as Mark Olen of Mentor pointed out “if Henry Ford had asked people what they wanted, they would have said faster horses”. So innovation is also required and Chris Brown of Broadcom set EDA companies the challenge of “collaborative competition” through standards. For example, UCIS has enabled TVS to build an innovative requirements sign off tool (asureSign) by reading verification data from multiple tools.
I was speaking with experts at Mentor about the latest developments in back-end physical verification (PV) and design-for-manufacturing (DFM). It prompted me to take a look at what has changed and what will be essential going forward. Here is what I see for this critical area for IC implementation.
First, we have passed the 28nm barrier and are already looking to a new generation of design. Leading-edge design starts are now at 20nm and we will see production silicon for that node by early 2013. However, in a new research brief, “Driving first-time silicon success across the IC ecosystem,” by Dr. Handel Jones, semiconductor analyst at IBS, the total number of design starts is not growing. While System integrators such as Samsung and Apple, are furiously growing their mobile businesses, the ability to integrate ever-larger collections of IP in their SOCs means they do not need to include more ICs in their phones to expand the features of their products. It is also true that 20nm designs have a much higher NRE than previous generations. Naturally, this economic incentive will keep some design starts at the 28nm and larger nodes.
Before I step on stage for a performance, I look at the crowd and say, “Lord, please don’t let me screw this up.” But it is the effort before this performance that really leads to this moment. First we have a casting process, where we try to find the best actor to play the lead, then the understudy, then the extras and technical team etc. This is usually done by a director, someone who has excelled at acting before, and develops the entire vision. Then we memorize our lines, this is the most mind-numbing and difficult part, so to prevent mental break downs, we divide the script up into smaller parts. We start with a few simple lines, then progressively add more lines and difficulty of memorization. Then we block the entire play, see what goes where, and perform it. Next, we have dress rehearsals, we get comfortable performing in our costumes and make sure things go off without a hitch. Now after all of this, we present it to the audience and hope that we don’t get pelted with tomatoes. After we perform, we wait for the audience to react, if they respond with cheers, we repeat the act the same way the next night with minor adjustments, if we are hurt and killed with articles of food, we then see what to improve and make changes for the next show.
Calypto has just published a new report on trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey. The survey was executed in late 2011 and had 744 SoC, IC, and FPGA design professionals respond; this report will analyze the survey results and identify relevant year-to-year trends.
By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65 nm and beyond.
The topics covered in this report are:
Survey methodology and demographics
Top methods used to reduce power
Percent of engineering time spent meeting power specifications
Top criteria for selecting RTL power optimization tools
Process nodes where RTL power optimization becomes important
Plans to implement power optimization tools in 2012
In a design ecosystem increasingly influenced by software and systems development, massive verification demands, and the boundaries of physics, engineers have a wonderful new set of problems to solve! Yet the principles they will use to innovate their way to exciting solutions and products remain as fundamental and universal as the reality of the Golden Ratio itself. With the aid of some of these principles, Aart talks about what new strategies and methodologies semiconductor players will need to achieve the critical mass necessary to craft productive and creative solutions within a design ecosystem complexity that surpasses anything seen yet in human history.
Click on the graphic to view the video.
Dr. Aart de Geus
CEO & Chairman of the Board
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Cadence Press just introduced a new title on Advanced Verification Topics by Bishnupriya Bhattacharya and contributors. Here is a small quote from what Adam Sherer, Cadence Product Marketing Director, said in the Preface to the book:
Consumers may perceive that “it’s a digital world,” but these advanced verification topics speak to the magic that goes on under the hood of every SoC. As verification engineering managers and team leaders, we know that MDV, multi-language VIP, low-power, mixed-signal, and acceleration topics are converging at 20 nm and beyond; but we don’t want to create whole new methodologies for each one. The authors of this book realized this, and selected the Accellera UVM standard as the common base from which to offer solutions that leverage reuse and raise team-level productivity. That’s why we have written this book—not only for verification engineers familiar with the UVM and the benefits it brings to digital verification, but also for verification engineers who need to tackle these advanced tasks. Though the solutions in this book are not standardized, most of them are available through open-source code. For all of you, the material in this Advanced Verification Topics book is provided as a means to stay productive and profitable in the face of growing verification complexity.
EDACafe has exclusive previews of the text by clicking on the links below.