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Intel Creates Neuromorphic Research Community to Advance ‘Loihi’ Test Chip

March 1st, 2018 by intel

Members will Receive Resources for Exploring Neuromorphic Computing Use Cases

By Dr. Michael Mayberry

This week, we hosted the Neuro Inspired Computational Elements (NICE) workshop at our Oregon campus with the goal of bringing together researchers from different scientific disciplines to discuss and explore the development of next-generation computing architectures, including neuromorphic computing. Today at the workshop, we provided an update on Intel’s neuromorphic research and announced a collaborative research initiative to encourage experimentation with our Loihi neuromorphic test chip.

Here’s a status of our neuromorphic computing efforts and details on this new research community.

Where We Are

Fabrication and packaging of our Loihi test chip was completed in early November, and we began power-on and validation. We were pleased to find 100 percent functionality, a wide operating margin and few bugs overall. Our small-scale demonstrations that we had prepared on our emulator worked as expected on the real silicon, though, of course, running orders of magnitude faster. Our equivalent of a “Hello World” application is recognizing a 3-D object from multiple viewing angles, structured after the COIL-20 example from Columbia University. As measured at our lab, this particular application uses less than 1 percent of Loihi, learns the training set in seconds and consumes tens of milliwatts.

We shared Loihi architectural details in a paper that IEEE Micro recently published, and we presented those details and several demos to NICE workshop attendees this week.

We have delivered the first developer systems to select research collaborators who are working on a variety of applications including sensing, motor control, information processing and more. Software development tools remain one of our focus areas, and we’re looking forward to running much larger scale applications in conjunction with research collaborators. As we learn more together, we expect progress to accelerate, and that’s where today’s announcement comes in.

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CES Panel: Autonomous Vehicles in the Cities of Tomorrow

January 18th, 2018 by Sanjay Gangal

Where do autonomous vehicles stand today and when will they be ready?  How will they operate in connected cities and will consumers be ready to use them? Listen to this panel of experts working on autonomy share their perspectives on the current and future state of self-driving technology.

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CES 2018 Press Conference: Qualcomm – Inventing the Path to 5G

January 17th, 2018 by Sanjay Gangal

Qualcomm President Cristiano Amon is at CES to showcase the company’s latest inventions that are leading the world to 5G in industries from IoT to automotive.

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Median Income of Electrotechnology, IT Professionals Rises to $130,000 for Largest Gain in Past Five Years

November 17th, 2015 by Sanjay Gangal

Article source: IEEE

Median income for electrotechnology and information technology professionals jumped by more than 4 percent in 2014, the largest increase in the past five years, according to the 2015 IEEE-USASalary & Benefits Survey.

Median incomes from primary sources — salary, commissions, bonuses and net self-employment income — for U.S. IEEE members working full-time in their primary area of technical competence (job specialty) rose from $124,700 in the 2013 tax year to $130,000 in 2014.

The 4.25 percent increase comes a year after median income rose by its small percentage over the past five years, .56 percent.

The results are based on survey responses from 10,215 people. Here are median incomes since 2009:

Tax Year Median Income % Increase
2009 $113,500
2010 $118,000 3.96
2011 $119,950 1.65
2012 $124,000 3.37
2013 $124,700 0.56
2014 $130,000 4.25

Those employed in communications technology once again enjoyed the highest median earnings ($150,000), followed by circuits and devices ($143,008) and signals and applications ($141,062).

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Asymptotic or Divergent: Three Verification Managers Look to the Future at DAC

May 5th, 2014 by Sanjay Gangal

What would the Design Automation Conference (DAC) be without a verification panel or two? This year, one in particular takes a look at a variety of verification technologies. Titled, “The Asymptote of Verification,” it will be moderated by Bryon Moyer of EE Journal and held Monday, June 2, from 5:15 p.m. until 6 p.m. in the Pavilion (Booth #313) on the exhibit floor.

Proposed and organized by Graham Bell of Real Intent, users make up the panel and include Brian Hunter of Cavium, Holger Busch at Infineon Technologies and Bill Steinmetz from NVIDIA. Special thanks go to Breker, OneSpin and Real Intent for securing these three experts who will share their real-world experiences with formal verification, static RTL analysis, and graph-based verification. Oh yes, they are users of Breker, OneSpin and Real Intent tools.

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The Dell Precision M2800 Mobile Workstation is Available to Help Inspire Innovation for Design Professionals and Students

May 1st, 2014 by Andy Rhodes

The evolution of digital content creation has unleashed the productivity of engineers, designers, creative professionals and students everywhere, but it has also set corresponding expectations incredibly high for that productivity as well, making it crucial for those individuals to use the proper tools to help their visions to come to life. Professional and aspiring engineers and designers cannot do their job these days without specialized applications for 3D modeling, digital content creation, and computer aided engineering and design such as Adobe Creative Cloud and AutoCAD. The problem is, for some, they’re being forced to run these applications on notebooks or desktops that don’t have enough power to generate the performance they need because they can’t afford a traditional workstation.

Dell Precision M2800

Dell Precision M2800

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Intel Engineer Reimagines Earbuds for Smartphones

April 18th, 2014 by Sanjay Gangal

 Article source: Intel Free Press

Engineer Indira Negi worked on the design of Intel smart earbuds

Indira Negi brings passion for running, biometric experience and maker skills to development of Intel smart earbuds.

When she literally jogged on-stage to join Intel CEO Brian Krzanich in his opening keynote at International CES in Las Vegas, engineer Indira Negi was there to demonstrate the Intel smart earbuds that she and her team had developed, but the “smart” design she showed off also helped solve an issue the avid runner had personally encountered.

Indira Negi at CES with Intel CEO Brian Krzanich demo Intel smart earbuds

“I am a runner — I get hives from the sun, I have to run with gloves on,” said Negi about running with a smartphone. “That means when there is a bad song, I have to take out my phone, take off my gloves, unlock my phone and change the song.”

Starting from solving a problem that she knew all too well, Negi, a sensors systems engineer in the Intel New Devices Group, and a team set out to create a device and software that would monitor heart rate and adjust music playback based on sensor feedback. The result was the Intel smart earbuds reference design, developed in collaboration with Valencell.

Negi’s study of bioelectronics and biosensors in graduate school — she earned a master’s degree in electrical engineering from Arizona State — lent her a keen appreciation of the value of biometric monitoring.

One project she worked on while at ASU measured stress levels in saliva using specially treated paper. When you are working out, you are stressing your body in a positive way, explained Negi. If you work out too hard, this becomes negative stress, which can increase the chances of getting injured. She also worked on molecular imprinted polymers while at ASU coated with biochemical sensors that reacted only to specific molecules.

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Will Verification Allow Time for Design?

December 2nd, 2013 by Sanjay Gangal

Article source: TVS

Design engineers are increasingly spending their time on verification. Research suggests that it is now more than 50% of their time and, according to Harry Foster of Mentor Graphics in his lighter moments, if we continue the current linear trend then it will reach 100% by 2030! So why is verification so demanding? It seems that IP reuse has enabled designers to create larger, more complex designs to keep pace with our manufacturing capability but our verification productivity has not kept pace.

Looking to tools for productivity gains, EDAC (the EDA Consortium) reported that the overall EDA verification market grew by 38% from 2010 to 2012 with emulation up by 94%. But, as Mark Olen of Mentor pointed out “if Henry Ford had asked people what they wanted, they would have said faster horses”. So innovation is also required and Chris Brown of Broadcom set EDA companies the challenge of “collaborative competition” through standards. For example, UCIS has enabled TVS to build an innovative requirements sign off tool (asureSign) by reading verification data from multiple tools.

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Topological insulators: Breaking symmetry for faster computers

November 25th, 2013 by Sanjay Gangal

Article Source: Tokyo Institute of Technology, Center for Public Information

A new compound developed at Tokyo Tech shows highly unusual conducting properties that could be used in future electronic components. The details are described in the November 2013 issue of Tokyo Institute of Technology Bulletin:

Ordinary insulating solids, such as diamond, have energy bands that are fully occupied by electrons. The conducting band is so far away from the valence band in diamond that electrons do not have sufficient energy to move – the ‘band gap’ is large – therefore no electric current can be carried.

In recent years, researchers have become interested in materials called topological insulators (TIs), which act as insulators on the inside, but are highly conductive on their surfaces. In TIs, an exceptionally strong spin-orbit interaction inverts the energy gap between occupied and empty states, so that electrons at the surface can flow across the gap. These properties are intrinsic to the material, meaning a TI remains conductive even if its surface is not perfect.

Now, an international team of scientists from Japan, the UK and the USA, led by Takao Sasagawa at Tokyo Institute of Technology, have successfully developed a new TI from bismuth, tellurium and chlorine (BiTeCl). Their new TI is inversion asymmetric, meaning it has different electronic states, and therefore different polarities, on each crystal surface. As a result, it exhibits many topological effects that have not been seen experimentally before.

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Unravelling the mind-body connection with power-efficient IC chip jointly developed by A*STAR IME, NTU and NUS

November 25th, 2013 by Sanjay Gangal

Article source: IME

Despite the advances in neuroscience research, the human brain remains a complex puzzle with questions unanswered on how it controls human behaviour, cognitive functions and movements.  Scientists from A*STAR Institute of Microelectronics (IME), Nanyang Technological University (NTU) and National University of Singapore (NUS) have jointly developed and demonstrated an integrated circuit (IC) chip with record-low power consumption for direct recording of brain activities. This breakthrough minimises the patient’s exposure to electromagnetic radiation and heat during the recording process, making it possible to integrate greater number of channels (>100 channels) to acquire more comprehensive profile of brain signals, paving the way to unlock the mystery behind the complex mind-body connection.

Neural recording system is a vital tool to acquire and process brain signals, and is also applied in artificial limb control (or neural prosthesis) treatments for paralyzed patients. The system comprises multiple electrodes for data acquisition and is implanted within the skull during the operation. The implantability of the system places tight limits on its size and power consumption, while at the same time demanding sufficient performance to record good quality data.

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