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Sanjay Gangal
Sanjay Gangal
Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999.

“Novel New Vertically-Oriented, Antifuse Non-Volatile Memory Bit Cell” by Harry Luan, CTO of Kilopass Technology

 
October 22nd, 2012 by Sanjay Gangal

Article source: Kilopass Technology

Harry Luan, chief technology officer at Kilopass Technology Inc., a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP) presenting “Novel New Vertically-Oriented, Antifuse Non-Volatile Memory Bit Cell” at MemCon 2012 on Tuesday, September 18, at 2:15 p.m. at the Santa Clara Convention Center, Santa Clara, Calif.

The new embedded VCM (Vertical Cross-point Memory) NVM IP bit cell quadruples the density of today’s anti-fuse NVM IP bit cell. The VCM bit cell will make possible program storage where today’s embedded non-volatile memory (eNVM) technology is cost-prohibitive or unavailable at capacities of 4Mb to 32Mb. It will also enable a higher level of performance more similar to SRAM compared to existing slower eNVM technologies or external flash or EEPROM chips.

eNVM is a method to store permanent data or software onto a standard chip using the industry-standard CMOS logic manufacturing process. The integration of eNVM helps to reduce cost, footprint, and power of the chip. However, until now eNVM has been limited to a 4Mb upper limit of capacity and limited erase cycles, also known as endurance. With the VCM bit cell technology, Kilopass will dramatically scale this limit to 32Mb with capability to scale beyond, thus providing more endurance.

“The VCM bit cell is an entirely new memory bit cell giving us an unprecedented memory density in standard logic processes from 180nm to the leading edge 20nm and beyond,” said Harry Luan, Chief Technology Officer at Kilopass Technology Inc. “Our R&D team fabricated the patent-pending VCM bit cell technology, which reduces the silicon area of the bit cell four fold, while contributing to improved performance, reduced dynamic power requirements, and greater endurance. Developed after more than four years from the inception of the concept in 2008 to today’s announcement, the new VCM bit cell will enable NVM IP to replace Serial Flash/EEPROMin applications that require execute-in-place and that must harvest power or run for extended periods between battery charges.”

About The VCMTM Bit Cell Technology

The VCM bit cell technology differs from that of the current Kilopass NVM IP, which requires a lateral selection transistor in planar (X-Y) directions to form memory bits. The VCM bit cell technology uses one single P-MOS transistor to both store and control the memory content. This compaction method reduces the footprint of the single bit cell from about 75 F2 for Kilopass’ current XPM memory to 12 F2 for VCM memory, where each F describes a manufacturable feature. By comparison, a typical embedded flash memory has an area of about 50 F2, and the state-of-the-art NAND flash bit cell with a fully customized memory process technology and extra cost can only achieve 6F2, about half of the area of the VCM bit cell. The VCM bit cell is the densest eNVM that exists in standard logic process.

VCM bit cell technology adds a simple processing step/mask that needs no new materials, equipment, or additional thermal cycles. An additional relatively coarse grade mask is used, which is inexpensive and easy to manufacture. Indeed, the VCM bit cell memory technology has been designed into a 110nm analog/mixed signal process in three different test shuttles with successful results. VCM bit cell technology is currently ready to be integrated into the upcoming Numera product in early 2013.

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Category: Kilopass

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