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 The Dominion of Design

Archive for September, 2012

The Measure of Nanometer Silicon Success

Monday, September 24th, 2012

I was speaking with experts at Mentor about the latest developments in back-end physical verification (PV) and design-for-manufacturing (DFM).  It prompted me to take a look at what has changed and what will be essential going forward. Here is what I see for this critical area for IC implementation.

First, we have passed the 28nm barrier and are already looking to a new generation of design. Leading-edge design starts are now at 20nm and we will see production silicon for that node by early 2013.  However, in a new research brief, “Driving first-time silicon success across the IC ecosystem,” by Dr. Handel Jones, semiconductor analyst at IBS, the total number of design starts is not growing.  While System integrators such as Samsung and Apple, are furiously growing their mobile businesses, the ability to integrate ever-larger collections of IP in their SOCs means they do not need to include more ICs in their phones to expand the features of their products.  It is also true that 20nm designs have a much higher NRE than previous generations.  Naturally, this economic incentive will keep some design starts at the 28nm and larger nodes.


S2C: FPGA Base prototyping- Download white paper

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