Calypto has just published a new report on trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey. The survey was executed in late 2011 and had 744 SoC, IC, and FPGA design professionals respond; this report will analyze the survey results and identify relevant year-to-year trends.
By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65 nm and beyond.
The topics covered in this report are:
Survey methodology and demographics
Top methods used to reduce power
Percent of engineering time spent meeting power specifications
Top criteria for selecting RTL power optimization tools
Process nodes where RTL power optimization becomes important
Plans to implement power optimization tools in 2012
In a design ecosystem increasingly influenced by software and systems development, massive verification demands, and the boundaries of physics, engineers have a wonderful new set of problems to solve! Yet the principles they will use to innovate their way to exciting solutions and products remain as fundamental and universal as the reality of the Golden Ratio itself. With the aid of some of these principles, Aart talks about what new strategies and methodologies semiconductor players will need to achieve the critical mass necessary to craft productive and creative solutions within a design ecosystem complexity that surpasses anything seen yet in human history.
Click on the graphic to view the video.
Dr. Aart de Geus
CEO & Chairman of the Board
The importance behind secure and fast file transfer plays a huge factor as it relates to the productivity within an engineering design workflow. Design engineers and semiconductor companies need to boost team collaboration through fast and secure content sharing around the globe to get their designs finalized and onto the chip manufacturer for creation.
Learn how to optimize the engineering design workflow and send your LARGE files faster with this new whitepaper:
Cadence Press just introduced a new title on Advanced Verification Topics by Bishnupriya Bhattacharya and contributors. Here is a small quote from what Adam Sherer, Cadence Product Marketing Director, said in the Preface to the book:
Consumers may perceive that “it’s a digital world,” but these advanced verification topics speak to the magic that goes on under the hood of every SoC. As verification engineering managers and team leaders, we know that MDV, multi-language VIP, low-power, mixed-signal, and acceleration topics are converging at 20 nm and beyond; but we don’t want to create whole new methodologies for each one. The authors of this book realized this, and selected the Accellera UVM standard as the common base from which to offer solutions that leverage reuse and raise team-level productivity. That’s why we have written this book—not only for verification engineers familiar with the UVM and the benefits it brings to digital verification, but also for verification engineers who need to tackle these advanced tasks. Though the solutions in this book are not standardized, most of them are available through open-source code. For all of you, the material in this Advanced Verification Topics book is provided as a means to stay productive and profitable in the face of growing verification complexity.
EDACafe has exclusive previews of the text by clicking on the links below.