A little over a month ago, Vaishnav Gorur of Real Intent published an article on Tech Forum with the title “Blindsided by a Glitch”.
The article provides good design guidelines while pointing out that following the guidelines is not always sufficient to avoid downstream problems. The article made me think about how dependent on EDA tools some designers can be to the point of allowing such tools to introduce design errors that are justifiable given the algorithms and rules pertaining to such tools.
In the early nineties, I had the opportunity to “experiment” with Design Compiler to find different semantics in both VHDL and Verilog to describe the same function but get different gate level circuits produced. At the beginning many results looked like bugs in the tool, but, as it turned out then and turns out today, logic synthesis does generate different circuitry depending on how the RTL is described.