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Gabe Moretti
Gabe Moretti
In June 2012 Gabe Moretti will celebrate 44 years in EDA. Gabe has contributed to the industry first as a developer, then as a senior manager and now as an editor and industry observer. He is a Senior member of the IEEE and the recipient of the IEEE RonWaxman Meritorious Award. Gabe has worked … More »

Daniel Nenni Shows His Marketing Skill

 
August 2nd, 2012 by Gabe Moretti

In a piece titled “SemiWiki.com Analytics Exposed” conveniently published on LinkedIn as well as its own masthead Daniel Nenni espoused the growth of his creation and compares it to other publications. You can read it at:
http://www.semiwiki.com/forum/content/1529-semiwiki-com-analytics-exposed.html

The piece has many problems, but I will just address what I find most egregious.

Why Alexa?

First of all let’s consider the source of the data. Alexa claims to be “The Web Information Company” but the title is self granted. I prefer Google Analytics, but of course that is a more secure site and not so generous with third party “data”. I ran an experiment the last three days to confirm or refute Daniel “numbers” as far as my site was concerned. What I got was extremely variable results with over 10% error among the queries. Thus my conclusion is that Alexa gives numbers, not qualified data. After all the free results are an invitation to pay for tools and services.

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Catapult LP Handles System Level Power Issues

 
July 10th, 2012 by Gabe Moretti

A few days before DAC Calypto announced Catapult Low-Power (LP), a high-level synthesis (HLS) tool that adds power as an optimization goal. Since August 2011, when Calypto received Catapult C from Mentor the company has integrated the tool within the ESL flow that includes SLEC, its equivalence checking tool, and now has also integrated a power analysis and evaluation function into the tool renamed simply Catapult.

I asked Shawn McCloud, VP of Marketing at Calypto, why the company had chosen to add power analysis to the HLS product. The answer, not surprisingly is not a simple one, as the decision was based on the results of a market survey conducted in the fall of 2011.

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Automatic Generation of SDC by Blue Pearl Software

 
July 6th, 2012 by Gabe Moretti

As electronics designers face increasing pressure to shorten the design cycle, the need for automatic generation of key design data increases. The penalty for missing the market window means financial losses for the company and at times, even the need to abandon that particular market. One of the ways to improve reliability and shorten development time is to increase the robustness of the relationship between RTL developers and place and route engineers. Synthesis is the key step in the process of transforming a RTL representation into a gate level one.

The manual method of writing Synopsys Design Constraints (SDC) data is often incomplete and causes a perceived need for “experimentation”. Blue Pearl’s product automatically generates a complete set of SDC timing exceptions significantly reducing the number of iterations for product development teams.

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Goldrush at the Denali Party, Interposers, and Sino-American Relations

 
June 26th, 2012 by Gabe Moretti

These and other subjects are covered in the most recent issue of Assembling the Future, the free newsletter you can subscribe to and read at www.gabeoneda.com.

It is likely the last revue you will read about DAC until next year and it comes together with other six articles about the conference. The issue covers the economics of 20 nm, software verification, 3D, standards, and other issues about DAC, including whether or not the Denali party should be retired. As I wrote in my article “Sanjay (Denali version) would have had the Goldrush at the party”.

The other articles in the issue are from Breker Verification talking about their experience as an exhibitor that “breaks systems”. Verification and what it is like to exhibit across the aisle from one of the “big 3” is the subject of the article from EVE.

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Zuken Innovation World Call For Papers Submission

 
June 19th, 2012 by Gabe Moretti

Zuken Innovation World is Zuken Americas annual conference and the company is seeking papers on this year’s theme of INNOVATION. Sharing first-hand knowledge and experience is a cornerstone of this conference and what makes it so successful. Amy Clements, conference manager told me that they are interested in papers that describe a breakthrough or a solution to a particular design challenge. The Zuken Innovation World 2012 conference will be held October 15-17 in Newport Beach, CA, a location that is hard to resist.

Zuken Innovation World conferences are premier annual events for the Zuken community. Held in locations around the globe, the conferences bring together customers and industry professionals in an environment that encourages networking, learning, and sharing of innovative ideas.

Providing an open environment for networking and partnership development is a key element of Zuken Innovation World. Partnerships with co-workers, other customers, industry professionals, and Zuken staff provide lasting benefits. People working together to solve common problems achieve greater success.

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Software Costs Up: This Is Not News

 
June 13th, 2012 by Gabe Moretti

Steve Leibson posted an article in the EDA360 Insider that reports on a panel at DAC chaired by Wally Rhines. The panel on ESL touched on the cost of IC development and Wally pointed out that the cost of software development is much higher than the one for hardware. In fact, software development costs are rising.

This should not come as a surprise to careful observers of the industry.

What is happening is that IC manufacturing costs are increasing significantly but hardware development costs have not been rising very much. Wally stated that the increase is around 10%. Re-use is the principal reason for the stability of hardware development cost. The use of standard cores, like those from ARM is so widespread that when combined with standard busses and functional blocks, most IC’s look more like standard computers than ASIC.

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Calypto Announces Catapult Low-Power High-Level Synthesis

 
May 31st, 2012 by Gabe Moretti

Calypto Design Systems, Inc. announced Catapult Low-Power (LP). For those that were wondering why Mentor had given Catapult-C to Calypto, and those who having accepted the transfer were wondering what in the world Calypto would do with it, the answer arrived today in the form of a product announcement.

To begin with it is clear how Catapult-C fits with the original Calypto products. I t is a link between ESL and RTL that is parallel to the SLEC product. But the new release is much more than that. It incorporates some of the SLEC technology as well as some of the PowerPro technology, providing a HLS that is also power aware.

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Synopsys and Mentor Report Operating Results

 
May 29th, 2012 by Gabe Moretti

Both Synopsys and Mentor reported their Operating Results within one week of each other. For Synopsys it was its second quarter results, while Mentor reported its first quarter results. Both companies had good quarters, although Synopsys, as it is to be expected, had better overall and relative results than Mentor.

Synopsys Is All Good News

There got to be an end: it is just not human! But I do not see any changes to Synopsys good news, quarter after quarter. It may be in the genes, it may be in the coffee, or it just may be in old fashioned good work. But first an outing then the numbers.

The Outing

I have had a relationship with Synopsys since 1990, never as an employee, but as an early user of Design Compiler, then as somewhat of a competitor, and finally as a professional observer. During all that time I have known Chi-Foon Chan who joined Synopsys in 1990 and until May 23rd was the President and COO of the company. I know relatively few people that knew that Chi-Foon even existed. He worked in the background, but worked very effectively. By comparison everyone knows who Greg Hinckley is at Mentor. I suppose that when one is in the same organization as Aart de Geus, it is not very difficult to stay in the background. But it takes a lot of stamina to do so and outperform expectations for a long time. Most people seek the lime lights, or at least their piece of sunshine. So Chi-Foon is out of the closet, and everyone now knows what I have experienced. Talk EDA with Aart or Chi-Foon and the result is the same.

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John Cooley Offers DAC Entertainment

 
May 24th, 2012 by Gabe Moretti

John Cooley just published the first group of “edgy” questions submitted for his troublemaker panel at DAC. I must say the questions are almost all relevant, but very few will be answered. All the questions related to lawsuits, all the questions related to market share, all the questions related to top users of a specific product, all questions related to possible acquisitions, and all questions that ask why executives of a particular company are apparently stupid will of course not be answered. So, the collection of questions is a very well thought out vehicle to let users and competitors blow out steam, but certainly not to shed light on the industry. This will be another “EDAC CEO Panel” style event. It may make for good entertainment, John is always entertaining, but will yield very little knowledge.

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Do What I Mean, Not What I Say

 
May 7th, 2012 by Gabe Moretti

A little over a month ago, Vaishnav Gorur of Real Intent published an article on Tech Forum with the title “Blindsided by a Glitch”.
The article provides good design guidelines while pointing out that following the guidelines is not always sufficient to avoid downstream problems. The article made me think about how dependent on EDA tools some designers can be to the point of allowing such tools to introduce design errors that are justifiable given the algorithms and rules pertaining to such tools.

In the early nineties, I had the opportunity to “experiment” with Design Compiler to find different semantics in both VHDL and Verilog to describe the same function but get different gate level circuits produced. At the beginning many results looked like bugs in the tool, but, as it turned out then and turns out today, logic synthesis does generate different circuitry depending on how the RTL is described.

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