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Can EDA Replicate Its 2011 Growth This Year?

Thursday, April 19th, 2012

Each quarter, the EDA Consortium publishes the Market Statistics Service (MSS) report containing detailed revenue data for the EDA industry. According to the latest information distributed by EDAC, overall fourth quarter 2011 EDA revenues increased 12.8% compared to the same period in 2010. Total revenue for Q4 was $1700.1 million. it is very interesting to me to note that the most authoritative research service covering EDA from the financial industry reports that revenues for the same period were $1.41 billion corresponding to an increase of 13% over the same period a year ago. There is clearly a discontinuity in the numbers.

EDAC can only use actual figures reported by its corporate members. Unfortunately for the consortium, Synopsys, a member, no longer shares its data with the organization and a few other large vendors of EDA tools are not members of EDAC. The result is that EDAC estimates the market contributions of important, non-reporting, companies and this can lead to inaccuracies. The error seems to be around 0.02% which is well within the acceptable error for forecasting purposes.

For the entire 2011 calendar year total EDA revenues were estimated to be $5.069 or 13.5% greater than 2010. The three largest companies (Cadence, Mentor, and Synopsys) account for approximately 75% of total revenue, while another half-a-dozen companies add another 13.6% to the total. Although 2012 appears to be a good year, growth will slow to a projected 7-8%.

Areas that will contribute significantly to the growth in revenue include: heterogeneous system designs, virtual prototyping, formal verification, emulation, power consumption analysis, and layout optimization.

The slowdown is due to two major factors: worldwide economy and a decrease in number of electronics companies using the very latest manufacturing process. (more…)

IP Business; VIP for NVM; Here comes the VIPER

Monday, March 26th, 2012

In January of 2011 I began the publication of a newsletter “Assembling the Future”.  With its March 2012 issue all readers of EDACafe can now access the newsletter for free.  Each month I will write a blog that describes the contents of that particular edition.  Just follow the link provided by EDACafe.  If you lose it then use this one:

This month’s topic is Intellectual Property (IP) and its necessary companion verification IP (VIP).   The first article written by Josh Lee of Uniquify presents a short history of the IP business, from its wild west origins to the still developing present days.  The second article, by David Hsu of Kilopass describes the relative large VIP package necessary to verify non-volatile memory (NVM) had macro IP.  Finally Neill Mullinger of Synopsys introduces the company’s new VIP family based on the VIPER architecture.

Next month’s topic is EDA standards.  How they are developed, why we need them, and what is on the horizon.  To contribute an article contact me at

A few thoughts about IP

The IP market needs not just IP cores, but also VIP functions and procedures, a way to find products, and standard procedures both commercial and technical.

The beginning of the IP market practically coincides with the commercial availability of logic synthesis.  In the late eighties and early nineties, Synopsys introduced a package of synthesizable basic logic modules called Designware while at the same time HDL Systems also started selling synthesizable cores written in both Verilog and VHDL.  HDL Systems later was assimilated by Philips semiconductors, victim of managerial incompetence.  But Synopsys persisted and leveraging its large installed base of Design Compiler grew its IP business to a very lucrative and growing business.  Its latest offering is based on the VIPER architecture described in this month’s issue of the newsletter. (more…)

DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

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