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Daniel Nenni Shows His Marketing Skill

Thursday, August 2nd, 2012

In a piece titled “ Analytics Exposed” conveniently published on LinkedIn as well as its own masthead Daniel Nenni espoused the growth of his creation and compares it to other publications. You can read it at:

The piece has many problems, but I will just address what I find most egregious.

Why Alexa?

First of all let’s consider the source of the data. Alexa claims to be “The Web Information Company” but the title is self granted. I prefer Google Analytics, but of course that is a more secure site and not so generous with third party “data”. I ran an experiment the last three days to confirm or refute Daniel “numbers” as far as my site was concerned. What I got was extremely variable results with over 10% error among the queries. Thus my conclusion is that Alexa gives numbers, not qualified data. After all the free results are an invitation to pay for tools and services.


Catapult LP Handles System Level Power Issues

Tuesday, July 10th, 2012

A few days before DAC Calypto announced Catapult Low-Power (LP), a high-level synthesis (HLS) tool that adds power as an optimization goal. Since August 2011, when Calypto received Catapult C from Mentor the company has integrated the tool within the ESL flow that includes SLEC, its equivalence checking tool, and now has also integrated a power analysis and evaluation function into the tool renamed simply Catapult.

I asked Shawn McCloud, VP of Marketing at Calypto, why the company had chosen to add power analysis to the HLS product. The answer, not surprisingly is not a simple one, as the decision was based on the results of a market survey conducted in the fall of 2011.


Automatic Generation of SDC by Blue Pearl Software

Friday, July 6th, 2012

As electronics designers face increasing pressure to shorten the design cycle, the need for automatic generation of key design data increases. The penalty for missing the market window means financial losses for the company and at times, even the need to abandon that particular market. One of the ways to improve reliability and shorten development time is to increase the robustness of the relationship between RTL developers and place and route engineers. Synthesis is the key step in the process of transforming a RTL representation into a gate level one.

The manual method of writing Synopsys Design Constraints (SDC) data is often incomplete and causes a perceived need for “experimentation”. Blue Pearl’s product automatically generates a complete set of SDC timing exceptions significantly reducing the number of iterations for product development teams.


Goldrush at the Denali Party, Interposers, and Sino-American Relations

Tuesday, June 26th, 2012

These and other subjects are covered in the most recent issue of Assembling the Future, the free newsletter you can subscribe to and read at

It is likely the last revue you will read about DAC until next year and it comes together with other six articles about the conference. The issue covers the economics of 20 nm, software verification, 3D, standards, and other issues about DAC, including whether or not the Denali party should be retired. As I wrote in my article “Sanjay (Denali version) would have had the Goldrush at the party”.

The other articles in the issue are from Breker Verification talking about their experience as an exhibitor that “breaks systems”. Verification and what it is like to exhibit across the aisle from one of the “big 3” is the subject of the article from EVE.


Zuken Innovation World Call For Papers Submission

Tuesday, June 19th, 2012

Zuken Innovation World is Zuken Americas annual conference and the company is seeking papers on this year’s theme of INNOVATION. Sharing first-hand knowledge and experience is a cornerstone of this conference and what makes it so successful. Amy Clements, conference manager told me that they are interested in papers that describe a breakthrough or a solution to a particular design challenge. The Zuken Innovation World 2012 conference will be held October 15-17 in Newport Beach, CA, a location that is hard to resist.

Zuken Innovation World conferences are premier annual events for the Zuken community. Held in locations around the globe, the conferences bring together customers and industry professionals in an environment that encourages networking, learning, and sharing of innovative ideas.

Providing an open environment for networking and partnership development is a key element of Zuken Innovation World. Partnerships with co-workers, other customers, industry professionals, and Zuken staff provide lasting benefits. People working together to solve common problems achieve greater success.


Software Costs Up: This Is Not News

Wednesday, June 13th, 2012

Steve Leibson posted an article in the EDA360 Insider that reports on a panel at DAC chaired by Wally Rhines. The panel on ESL touched on the cost of IC development and Wally pointed out that the cost of software development is much higher than the one for hardware. In fact, software development costs are rising.

This should not come as a surprise to careful observers of the industry.

What is happening is that IC manufacturing costs are increasing significantly but hardware development costs have not been rising very much. Wally stated that the increase is around 10%. Re-use is the principal reason for the stability of hardware development cost. The use of standard cores, like those from ARM is so widespread that when combined with standard busses and functional blocks, most IC’s look more like standard computers than ASIC.


Calypto Announces Catapult Low-Power High-Level Synthesis

Thursday, May 31st, 2012

Calypto Design Systems, Inc. announced Catapult Low-Power (LP). For those that were wondering why Mentor had given Catapult-C to Calypto, and those who having accepted the transfer were wondering what in the world Calypto would do with it, the answer arrived today in the form of a product announcement.

To begin with it is clear how Catapult-C fits with the original Calypto products. I t is a link between ESL and RTL that is parallel to the SLEC product. But the new release is much more than that. It incorporates some of the SLEC technology as well as some of the PowerPro technology, providing a HLS that is also power aware.


John Cooley Offers DAC Entertainment

Thursday, May 24th, 2012

John Cooley just published the first group of “edgy” questions submitted for his troublemaker panel at DAC. I must say the questions are almost all relevant, but very few will be answered. All the questions related to lawsuits, all the questions related to market share, all the questions related to top users of a specific product, all questions related to possible acquisitions, and all questions that ask why executives of a particular company are apparently stupid will of course not be answered. So, the collection of questions is a very well thought out vehicle to let users and competitors blow out steam, but certainly not to shed light on the industry. This will be another “EDAC CEO Panel” style event. It may make for good entertainment, John is always entertaining, but will yield very little knowledge.


Do What I Mean, Not What I Say

Monday, May 7th, 2012

A little over a month ago, Vaishnav Gorur of Real Intent published an article on Tech Forum with the title “Blindsided by a Glitch”.
The article provides good design guidelines while pointing out that following the guidelines is not always sufficient to avoid downstream problems. The article made me think about how dependent on EDA tools some designers can be to the point of allowing such tools to introduce design errors that are justifiable given the algorithms and rules pertaining to such tools.

In the early nineties, I had the opportunity to “experiment” with Design Compiler to find different semantics in both VHDL and Verilog to describe the same function but get different gate level circuits produced. At the beginning many results looked like bugs in the tool, but, as it turned out then and turns out today, logic synthesis does generate different circuitry depending on how the RTL is described.


Standards: Past, Present, and Future

Monday, April 30th, 2012

Standards have, are, and will play a major role in EDA. The difficulties inherent in developing semiconductors require the existence of point tools that provide specific solutions to very demanding problems. These tools must be able to work together in an integrated flow that needs the ability to exchange data in a reliable manner. In addition engineers need to be able to exchange tools from various vendors for both technical and commercial reasons. All of these would not be possible without standards. To read more about standards go to


Our industry recognized the need for standards even before it became Electronic Design Automation. It was still called CAD, for Computer Aided Design, when, shortly after the introduction of proprietary workstations, users found the need to exchange schematic drawings among various workstations. EDIF was the result of this standardization exercise, but we soon discovered that a standard by itself is not very useful. All the workstation companies quickly develop EDIF readers, but you could not find an EDIF writer from any of them. Reality has a way of asserting itself, though. EDIF 1.0 became a format for storing designs that could be reused and thus, ultimately ported to a new system.


ClioSoft at DAC
TrueCircuits: IoTPLL

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