Gabe's EDA Update
In June 2012 Gabe Moretti will celebrate 44 years in EDA. Gabe has contributed to the industry first as a developer, then as a senior manager and now as an editor and industry observer. He is a Senior member of the IEEE and the recipient of the IEEE RonWaxman Meritorious Award. Gabe has worked … More »
The Approaching Discontinuity
December 3rd, 2012 by Gabe Moretti
The world of EDA is about to change. The subtle signs are there for all to see, and the coming reality is so different to be scary to some. Thus better not to talk about it. The changes will include how ICs are designed, developed, and verified. They will involve designers, tools developers, and manufacturers, and force an integration that the EDA industry has not experienced so far.
I have followed with great interest the various press releases from TSMC, Cadence, Mentor, and Synopsys describing the work, and the progress, toward finalizing a commercial grade 20 nm process. It is interesting that the vast majority of the news is about TSMC. There is a perplexing lack of news from other foundries about their work on the 20 nm process. Thus the question: are they already done or are they lagging behind?
I tend toward the second explanation. Accustomed to moving from one processing node to the next with regularity, I believe that most commercial foundries have been caught by surprise by the increased difficulty that the 20 nm process holds. it is not just a matter of developing a cell library, or to create and calibrate a new nanolithography process.
What the EDA companies and TSMC have found is that the processes of design and of manufacturing can no longer be considered as two separate methods. The traditional development of a new process was sequential and stand alone, while the new one reveals itself to require non-trivial feedback loops among the foundry and the EDA companies. So far it looks like we have managed to avoid getting the designer involved, although not for long.
Traditionally the foundry developed a cell library and a set of design rules. Of course the design rules have become more numerous and more complex with each new process. Then the EDA companies, using these as input, went to work to either improve existing algorithms or invent new ones that would allow designers to develop circuitry to be manufactured with the new process. The goal of developers was to start with an architectural concept driven by market requirements and end with a layout that could be manufactured using both new circuitry built with the cell library and re-used IP.
The responsibilities were well defined and delimited. Designers had the responsibility to design and develop circuitry that performed the desired functions within specified physical characteristics. EDA companies had the task to develop and support computer based tools that allowed the synthesis of circuitry so that it could be laid out and verified, again using EDA tools, ready for manufacturing, and that provided a way to verify that the tasks were done without errors. The foundry had the task to manufacture the devices with acceptable yields. In the end all made a profit while working in well defined areas of expertise.
Overflowing the Boundaries
As the traditional methods began to be employed to support the 20 nm process, it soon became obvious that such clean demarcation of responsibilities could not be maintained. For one thing the design rules became so complex using the established method to significantly impact productivity, and thus profitability. Transforming a design into a manufacturable layout now requires more knowledge of the manufacturing process than ever before. And, on the other hand, developing a cell library and a set of design rules requires more knowledge of the development process than before. Thus the work of the foundry and the EDA companies had to be more integrated than ever before.
The issue is no longer can we implement algorithms that respect the design rules without asking designers to know more than they are prepared to know about semiconductors physics and manufacturing without changes to the manufacturing process? The answer turns out to be negative. The manufacturing process is no longer a given. It must be developed with the knowledge of what it is possible to do with EDA tools in a profit making environment.
Obviously, given infinite time and resources, the problem is solvable. But the semiconductors industry is now fueled by consumers products. These are notoriously low margin products that require relatively short development times and large volume of product in order to be successful. Short development time means that the process of transforming an idea into a layout must be performed by average engineers in the shortest amount of time, generally 9 to 12 months. And the resulting circuitry must be manufacturable with yields that will result in a profit margin sufficient to assure a return on investment that is competitive.
The result is that professional staffs from EDA companies and foundries have had to work together more than ever in order to explore and test tradeoffs necessary to make sure that the entire method, from product architecture to IC packaging, is reliable. This has been a learning process, thus it is taking longer than usual and it is costing more than expected.
The result is that we will have products manufactured with the 20 nm process, but they will cost more to design, develop, and manufacture. End users will have to pay more for the additional functionality, breaking a pattern of more functionality for the same price that has become the norm with electronics products.
Although a first reading all this seems like bad news, it is actually very good news. The reason is that this new development method is a reliable introduction to what will be required to develop and support the 14 nm process. The task of using UV photolithography at the required resolution may in fact be so complicated to finally force the industry to invest in new manufacturing technologies. If not, given the staggering costs of such transformation, new methods that integrate design, development, and manufacturing will have to be developed.
The interaction between development, tools providers, and foundries is becoming a requirement. To some extent this is true at 20 nm, but it will be the norm at 14 nm. Verification is the aspects of product development that will see this impact the most. But using traditional verification methods will not be enough. They will generate tasks that are either too complex or too time consuming to be practical.
It is a well known and widely discussed fact that Verification is the most expensive portion of a design project. And, in many respects, it is also the most difficult to achieve correctly. Traditionally we have taken a cops and robbers approach to verification. We employ to different teams, one for development and one for verification. Generally, although not always, junior staff is assigned the verification tasks. This goes to the point that in some companies development is done in the US while verification is done in a developing country in order to lower costs.
Verification must be integrated in the development tool itself. Synopsys, in my opinion, has shown itself to be a visionary when it invested in both Springsoft and EVE, two companies that know a lot about verification. Development tools must become smarter, must understand the sources of errors. Just like formal analysis techniques make use of assertions generated by engineers, tools will have to be able to infer their own set of assertions and build correct by construction circuitry. The identification of errors will be directed by the set of design rules from the foundry, thus every tool will have to use a set of assertions that are foundry specific.
Whether an EDA company chooses to have one configurable tool or a set of foundry specific tools will depend mostly on the run time profile of the tool. The version that takes less memory and executes fastest will be the chosen solution.
Financial consideration may transform emulation boxes into intelligent peripherals that are integrated into a simulation environment that can handle multiple levels of abstraction. We must achieve a general purpose verification environment that avoids special purpose hardware. The latter is just to costly and has lower profit margins than software.
Stand alone verification tools will continue to exists for a time while the integration process evolves, but the history of EDA has shown that the tendency is toward more intelligent tools. The purpose is not only to make the work of a designer shorter by improving execution speed, but to make the designers more productive by guiding the process in error avoidance. The goal is not to help an engineer create the largest possible amount of errors in the shortest time possible, but to avoid errors in the shortest feasible amount of time.
The 14 nm Team
All development done at 14 nm will involve a team that includes development engineers, tools providers, process and manufacturing engineers. There is no other possible approach. The manufacturing flow and characteristics will dictate what is possible to build.
It will be too costly to design a circuit that cannot be built and try to fix it at the back end. The product must be architected knowing what can be built. That means the choice of third party IP will be restricted, in fact internal re-use may become more expensive, requiring a stricter selection and at times a significant re-design.
As I just wrote, EDA tools will have to be adapted to the specific constraints of the foundry and may be to the methods used by the development team. The key words “design for manufacturing” and “design for yield” will actually mean something more than developing a robust design. They will mean developing a design that can be successfully manufactured with the proprietary dialect of the 14 nm process “spoken” by the specific foundry.
Process development will have to take into account common circuitry and insure that those collections of transistors and connections will execute without generating parasitic effects that inhibit proper execution. The cell library will look more like a collection of macros not primitives. Proximity effects will be important and generate new layout considerations that will impact both timing and power features.
Clearly companies will try to minimize the cost of new hardware by using software as the “tailoring” ingredient in the recipe. EDA companies have already put increased resources in supporting software integration, but more needs to be done. Specifically the way to measure architectural tradeoff results must be improved.
Although each company will still be focused in performing its own mission, the final device will be the product of a consortium of specific companies. Grand alliances will be formed and, I fear, smaller companies will be the one suffering from this. Leading edge technology in EDA will be the province of companies with access to large amount of investments and established business partners. But, it must also be said, the number of electronics vendors who will be able to use the 14 nm process will be limited both by cost and by business reasons. There will be the need to develop a new business model that assures the proper return to EDA vendors, not just electronics companies and foundries. EDA cannot continue to be squeezed in the middle.
Smaller EDA companies will find good business opportunity serving the vast majority of producers who will continue to use 65 to 32 nm processes. Productivity improvements that lower costs at proven process nodes will offer opportunities to both established and new small EDA companies.