The world of EDA is about to change. The subtle signs are there for all to see, and the coming reality is so different to be scary to some. Thus better not to talk about it. The changes will include how ICs are designed, developed, and verified. They will involve designers, tools developers, and manufacturers, and force an integration that the EDA industry has not experienced so far.
I have followed with great interest the various press releases from TSMC, Cadence, Mentor, and Synopsys describing the work, and the progress, toward finalizing a commercial grade 20 nm process. It is interesting that the vast majority of the news is about TSMC. There is a perplexing lack of news from other foundries about their work on the 20 nm process. Thus the question: are they already done or are they lagging behind?
I tend toward the second explanation. Accustomed to moving from one processing node to the next with regularity, I believe that most commercial foundries have been caught by surprise by the increased difficulty that the 20 nm process holds. it is not just a matter of developing a cell library, or to create and calibrate a new nanolithography process.