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Gabe Moretti
Gabe Moretti
In June 2012 Gabe Moretti will celebrate 44 years in EDA. Gabe has contributed to the industry first as a developer, then as a senior manager and now as an editor and industry observer. He is a Senior member of the IEEE and the recipient of the IEEE RonWaxman Meritorious Award. Gabe has worked … More »

Synopsys and Tektronix Offer New New FPGA-Based Prototyping Solutions

 
November 13th, 2012 by Gabe Moretti

Increasing design complexity is posing heighten verification complexity. Most of the consumer electronic products that are pushing vendors toward state of the art processes require real time responses. These applications cannot be debugged using software based tools. Thus the use of FPGAs for SoC verification has become the norm.

In the last two weeks both Synopsys and Tektronix have introduced new powerful verification solutions to aid engineers developing SoC devices.

Synopsys

Synopsys announced the availability of Synopsys’ HAPS®-70 Series FPGA-based prototyping systems, extending its HAPS product line to address the increasing size and complexity of system-on-chip (SoC) designs. Taking full advantage of the technology originally gained with the Synplicity acquisition, the new product offers superior mapping and debugging capabilities when combined with the Certify, Synplify and Identify software tools.

The modular architecture of the HAPS-70 systems enables engineers to use a common prototyping environment for IP and SoC software development, hardware/software integration and system validation, reducing duplication of effort across projects. New “HAPS-aware” features of Synopsys’ Certify multi-FPGA prototyping software increase prototyping productivity by up to 10x with patent-pending algorithms to automate logic partitioning and live hardware queries to ease system bring-up compared to manual partitioning methods. The new prototyping systems also support HAPS Deep Trace Debug for greater debugging efficiency, providing approximately 100 times more signal storage capacity than the traditional memory storage employed by on-chip FPGA logic debuggers.

The HAPS-70 systems provide tightly integrated prototyping software and hardware, including high-speed time-domain multiplexing (HSTDM) technology, which in combination with new HapsTrak 3 I/O connectors delivers up to 3x prototype performance improvement over traditional connector and pin multiplexing technology. The new prototyping systems take advantage of a scalable architecture and the latest generation Xilinx Virtex-7 FPGA devices to support a wide range of design sizes with capacities from 12 to 144 million ASIC gates.

The flexibility and matched pin connections between the Virtex-7’s I/O banks and HapsTrak 3 connectors enable HAPS users to utilize I/O bandwidth where it is needed most while minimizing the number of unused pins. The modular architecture provides flexibility and a predictable growth path for the customer. The HAPS-70 FPGA-based prototyping systems are available now to early adopters in nine model variants, with capacities from 12 to 144 million ASIC gates: HAPS-70 S12, HAPS-70 S24, HAPS-70 S36, HAPS-70 S48, HAPS-70 S60, HAPS-70 S72, HAPS-70 S96, HAPS-70 S120 and HAPS-70 S144, where S denotes ASIC Gate count supported.

For easier system validation and software development, DesignWare Interface IP such as USB 3.0, PCI Express® and HDMI are validated on HAPS systems. With pre-validated DesignWare IP on HAPS systems and a rich selection of daughter cards for common IP protocols, designers can start software development earlier in the product development cycle and reduce IP integration effort.

Synopsys’ Universal Multi-Resource Bus (UMRBus) host connectivity option for the HAPS-70 system has been enhanced to support up to 400 MB/s bandwidth. The UMRBus provides a seamless link between HAPS-70 systems and Synopsys’ Virtualizer-based virtual prototypes to create an integrated hybrid prototyping environment for early software development and hardware/software integration. The UMRBus also provides remote access, a generic C++/TCL programming interface and co-simulation with Synopsys’ VCS® functional verification solution along with hierarchical block level bring-up and debug, enabling the HAPS-70 system to be incorporated into the design flow earlier.

To view the multimedia news release, please go to: http://www.synopsys.com/Company/PressRoom/Pages/haps70-news-release.aspx

Tektronix

Building on its leadership in electronic instrumentation for development egineers, Tektronix introduced its own FPGA based SoC development system, the Certus 2.0 abut two weeks ago. Following the acquisition of Veridae Systems last year, Tektronix Embedded Instrumentation solutions reflect the growing importance of Electronic Design Automation (EDA) software in helping engineers solve difficult instrumentation and debug challenges. As the release of a new version of Certus demonstrates, Tektronix is committed to strategic investment in EDA software-driven debug automation solutions that enable the validation of correct operation and the determination of the root cause of any issues faster in a unified and productive environment.

A suite of software and RTL-based embedded instruments, Certus 2.0 fundamentally changes the ASIC prototyping flow by enabling full RTL-level visibility and making FPGA internal visibility a feature of the prototyping platform. By using Certus 2.0 to pre-instrument up to one hundred thousand signals per FPGA device, designers gain comprehensive RTL-level signal visibility without time consuming synthesis and place and route cycles, allowing complex problems to be pinpointed and resolved quickly.

Certus 2.0 allows designers to automatically instrument all the signals likely to be needed in each of the FPGAs in a multi-FPGA ASIC prototype with a small FPGA LUT impact. This enables a proactive debug and instrumentation strategy, eliminating the need to re-compile the FPGA to debug each new behavior, typically a painful eight to eighteen hour ordeal with traditional tools. Other key capabilities include:

  • Automatic identification and instrumentation of RTL signals based on type and instance name including flip-flops, state machines, interfaces and enumerated types
  • On-chip, at-speed capture and compression of many seconds of data without special external hardware or consuming FPGA I/O resources
  • Advanced on-chip triggering bringing the power of logic analyzer trigger methods to embedded instrumentation
  • Time-correlated capture results across clock domains and multiple FPGAs providing a system-wide view of the entire target design

Certus 2.0 works on any existing commercial or custom ASIC prototyping platform, and does not need special connectors, cables, or external hardware. In addition, Certus 2.0 does not limit the operating speed of the prototype platform.

The Certus 2.0 ASIC prototyping debug solution is available now and is priced at $19,500 U.S. MSRP for a one year term-based floating license.

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One Response to “Synopsys and Tektronix Offer New New FPGA-Based Prototyping Solutions”

  1. Rick Bert says:

    This is interesting that there are still new entries into this crowded market. And, that Synopsys being owner of key patents in this area lets this happen.

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