Open side-bar Menu
 Gabe's EDA Update
Gabe Moretti
Gabe Moretti
In June 2012 Gabe Moretti will celebrate 44 years in EDA. Gabe has contributed to the industry first as a developer, then as a senior manager and now as an editor and industry observer. He is a Senior member of the IEEE and the recipient of the IEEE RonWaxman Meritorious Award. Gabe has worked … More »

Catapult LP Handles System Level Power Issues

July 10th, 2012 by Gabe Moretti

A few days before DAC Calypto announced Catapult Low-Power (LP), a high-level synthesis (HLS) tool that adds power as an optimization goal. Since August 2011, when Calypto received Catapult C from Mentor the company has integrated the tool within the ESL flow that includes SLEC, its equivalence checking tool, and now has also integrated a power analysis and evaluation function into the tool renamed simply Catapult.

I asked Shawn McCloud, VP of Marketing at Calypto, why the company had chosen to add power analysis to the HLS product. The answer, not surprisingly is not a simple one, as the decision was based on the results of a market survey conducted in the fall of 2011.

Over 40 percent of respondents stated their organizations were planning to evaluate or implement RTL power optimization tools in 2012. This high proportion indicates a growing trend to initiate more power optimization focus at the RTL rather than waiting until the later stages of design where far less impact on power can be made. The top factors that the design community cites for selecting an RTL power optimization tool are maximizing power reduction with minimum timing and area impact, and the accuracy of RTL power analysis. The top methods used to reduce power are clock gating and power gating.

Engineers spend an average of one-quarter of their time (26%) trying to meet power specifications. For a 50 person engineering team with a cost of $10 million per year, the 26 percent additional overhead on designers’ time associated with power management issues equates to $2.6M annually.

A majority of respondents said that RTL power optimization tools became critical at 65 nm and below. This is likely due to the diminishing supply voltage scaling at smaller nodes and the demand for higher performance/clock rates and stringent power and thermal budgets. This combination of factors is forcing designers to introduce aggressive power reduction and management techniques during RTL design as they go to lower process geometries.

Catapult LP

The new product is not the only tool from Calypto that deals with power issues. In fact Catapult LP is a perfect example of how an existing tool from a third party should be integrated with existing technology. Before obtaining Catapult C from Mentor, Calypto developed SLEC and PowerPro. The first one is a C to RTL verification platform that uses proprietary equivalence checking algorithms, while the latter is a RTL power analysis tool for peak, average, and toggle power utilization.

Thus when looking at the entire offering a user can use Catapult for ESL design and translation to RTL, Catapult LP for analyzing and planning power at the architectural level, SLEC to verify the equivalence of the description at ESL and RTL, and Power Pro to deal with power at the RTL.

The majority of low-power transformations today work at the gate level. Little automation exists at RTL and above, yet the opportunities to save power are the highest at ESL and RTL. One just has to apply the principal law of design: it is cheaper (and often easier) to avoid a problem than to correct it.

Using Catapult LP designers can explore various solutions in a technology independent, architecture neutral environment. Scenarios can be built to evaluate latency versus area, power versus performance, the use of memories versus registers, and sequential or parallel design. Working at ESL with Catapult LP, all this analysis can be done modifying constraints and not the design itself.

With Catapult LP engineers can reduce power through interactive exploration, analysis, and optimization. Power reports are built in Catapult LP showing power consumption, power savings, and the results of clock gating efficiency analysis.

Low power design constraints usually address four factors: battery life, power integrity, thermal integrity, and technology scaling with respect to leakage and dynamic power. Clearly Catapult LP does not directly deal with thermal integrity, but it can be used to easily modify circuit characteristics as a result of thermal analysis.

Overall Catapult LP is an impressive accomplishment by Calypto, both because it shows the ability of integrating a third party technology into an existing proprietary one, and because allows architects to deal with power issues in a manner that is directly integrated with a design description ready for logic synthesis.

Related posts:

Leave a Reply

DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise