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Archive for July, 2012

Catapult LP Handles System Level Power Issues

Tuesday, July 10th, 2012

A few days before DAC Calypto announced Catapult Low-Power (LP), a high-level synthesis (HLS) tool that adds power as an optimization goal. Since August 2011, when Calypto received Catapult C from Mentor the company has integrated the tool within the ESL flow that includes SLEC, its equivalence checking tool, and now has also integrated a power analysis and evaluation function into the tool renamed simply Catapult.

I asked Shawn McCloud, VP of Marketing at Calypto, why the company had chosen to add power analysis to the HLS product. The answer, not surprisingly is not a simple one, as the decision was based on the results of a market survey conducted in the fall of 2011.


Automatic Generation of SDC by Blue Pearl Software

Friday, July 6th, 2012

As electronics designers face increasing pressure to shorten the design cycle, the need for automatic generation of key design data increases. The penalty for missing the market window means financial losses for the company and at times, even the need to abandon that particular market. One of the ways to improve reliability and shorten development time is to increase the robustness of the relationship between RTL developers and place and route engineers. Synthesis is the key step in the process of transforming a RTL representation into a gate level one.

The manual method of writing Synopsys Design Constraints (SDC) data is often incomplete and causes a perceived need for “experimentation”. Blue Pearl’s product automatically generates a complete set of SDC timing exceptions significantly reducing the number of iterations for product development teams.


S2C: FPGA Base prototyping- Download white paper

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