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Archive for May, 2012

Calypto Announces Catapult Low-Power High-Level Synthesis

Thursday, May 31st, 2012

Calypto Design Systems, Inc. announced Catapult Low-Power (LP). For those that were wondering why Mentor had given Catapult-C to Calypto, and those who having accepted the transfer were wondering what in the world Calypto would do with it, the answer arrived today in the form of a product announcement.

To begin with it is clear how Catapult-C fits with the original Calypto products. I t is a link between ESL and RTL that is parallel to the SLEC product. But the new release is much more than that. It incorporates some of the SLEC technology as well as some of the PowerPro technology, providing a HLS that is also power aware.

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Synopsys and Mentor Report Operating Results

Tuesday, May 29th, 2012

Both Synopsys and Mentor reported their Operating Results within one week of each other. For Synopsys it was its second quarter results, while Mentor reported its first quarter results. Both companies had good quarters, although Synopsys, as it is to be expected, had better overall and relative results than Mentor.

Synopsys Is All Good News

There got to be an end: it is just not human! But I do not see any changes to Synopsys good news, quarter after quarter. It may be in the genes, it may be in the coffee, or it just may be in old fashioned good work. But first an outing then the numbers.

The Outing

I have had a relationship with Synopsys since 1990, never as an employee, but as an early user of Design Compiler, then as somewhat of a competitor, and finally as a professional observer. During all that time I have known Chi-Foon Chan who joined Synopsys in 1990 and until May 23rd was the President and COO of the company. I know relatively few people that knew that Chi-Foon even existed. He worked in the background, but worked very effectively. By comparison everyone knows who Greg Hinckley is at Mentor. I suppose that when one is in the same organization as Aart de Geus, it is not very difficult to stay in the background. But it takes a lot of stamina to do so and outperform expectations for a long time. Most people seek the lime lights, or at least their piece of sunshine. So Chi-Foon is out of the closet, and everyone now knows what I have experienced. Talk EDA with Aart or Chi-Foon and the result is the same.

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John Cooley Offers DAC Entertainment

Thursday, May 24th, 2012

John Cooley just published the first group of “edgy” questions submitted for his troublemaker panel at DAC. I must say the questions are almost all relevant, but very few will be answered. All the questions related to lawsuits, all the questions related to market share, all the questions related to top users of a specific product, all questions related to possible acquisitions, and all questions that ask why executives of a particular company are apparently stupid will of course not be answered. So, the collection of questions is a very well thought out vehicle to let users and competitors blow out steam, but certainly not to shed light on the industry. This will be another “EDAC CEO Panel” style event. It may make for good entertainment, John is always entertaining, but will yield very little knowledge.

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Do What I Mean, Not What I Say

Monday, May 7th, 2012

A little over a month ago, Vaishnav Gorur of Real Intent published an article on Tech Forum with the title “Blindsided by a Glitch”.
The article provides good design guidelines while pointing out that following the guidelines is not always sufficient to avoid downstream problems. The article made me think about how dependent on EDA tools some designers can be to the point of allowing such tools to introduce design errors that are justifiable given the algorithms and rules pertaining to such tools.

In the early nineties, I had the opportunity to “experiment” with Design Compiler to find different semantics in both VHDL and Verilog to describe the same function but get different gate level circuits produced. At the beginning many results looked like bugs in the tool, but, as it turned out then and turns out today, logic synthesis does generate different circuitry depending on how the RTL is described.

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