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Gabe Moretti
Gabe Moretti
In June 2012 Gabe Moretti will celebrate 44 years in EDA. Gabe has contributed to the industry first as a developer, then as a senior manager and now as an editor and industry observer. He is a Senior member of the IEEE and the recipient of the IEEE RonWaxman Meritorious Award. Gabe has worked … More »

Standards: Past, Present, and Future

 
April 30th, 2012 by Gabe Moretti

Standards have, are, and will play a major role in EDA. The difficulties inherent in developing semiconductors require the existence of point tools that provide specific solutions to very demanding problems. These tools must be able to work together in an integrated flow that needs the ability to exchange data in a reliable manner. In addition engineers need to be able to exchange tools from various vendors for both technical and commercial reasons. All of these would not be possible without standards. To read more about standards go to http://www.gabeoneda.com/newsletter/pdf/2012/04.

Past

Our industry recognized the need for standards even before it became Electronic Design Automation. It was still called CAD, for Computer Aided Design, when, shortly after the introduction of proprietary workstations, users found the need to exchange schematic drawings among various workstations. EDIF was the result of this standardization exercise, but we soon discovered that a standard by itself is not very useful. All the workstation companies quickly develop EDIF readers, but you could not find an EDIF writer from any of them. Reality has a way of asserting itself, though. EDIF 1.0 became a format for storing designs that could be reused and thus, ultimately ported to a new system.

Since then, the EDA industry has develop dozens of standards ranging from design entry languages, to synthesis syntax and semantics, to various physical description formats and languages. One standard that did not start out as an industry standard, but became one by default is the GDS-II format. It was developed by Calma in order to drive the Gerber photo plotting equipment used to prepare masks for photo lithography. It was never meant to last over forty years, but it is still used today. There have indeed been attempts at developing a more modern format with syntax and semantics extensions to deal with today’s requirements, but GDS-II is still the format of choice.

Some standard are developed from scratch following a requirements document, VHDL is the most famous of them, while others are developed starting with a popular existing solution, like Verilog for example. It is interesting that the requirement document for VHDL did not ask for a design language, but for a documentation language. Once the standard was complete, a company Vantage Computer Systems decided that the language could be simulated, and thus used to develop an electronic system. it was a good intuition that created a market that is still quite robust today.

In the eighties and early nineties the Design Automation Standards Committee (DASC) of the IEEE was the major body for the development of EDA standards. During the present century the DASC has lost some of its importance as a development body and that role has been taken up by industry consortia. The two most active in standard development are Si2 and Accellera, now renamed Accellera Systems Initiative.

Present

The two organizations have different operating methods and as a result, the Si2 standards are seldom offered to the IEEE for standardization, while all of the standards developed by Accellera are submitted to the IEEE and follow this organization approval and maintenance procedures.

Si2 has five major projects and another two activities that support projects that have terminated their engineering work and are ready to address new industry requirements as the result of evolving technology. These are the Open Modeling project and the LEF/DEF distribution of the specification.

Certainly the most popular Si2 project is the OpenAccess Coalition that this year celebrates its tenth anniversary. Started with a donation by Cadence of an API for its data base, this work is directly or indirectly responsible for many startups in the industry. Startups that targeted specific engineering areas within the EDA flow found a ready made integration path that would support the adoption of their specific product within an existing design flow, as long as it used the Cadence data base. Although it is not clear whether or not Cadence ever benefitted from this strategy, once the offer was made and the technology was part of Si2, it was too late to rethink the strategy.

It can be said, though, that Cadence direct competitors, Magma, Mentor, and Synopsys, have not adopted the OpenAccess data base as their internal data format, nor have they lost significant business as the result of their engineering choice.

Two other projects, Design for Manufacturability and OpenPDK, address back end flow requirements that have attracted significant attention by both foundries and EDA vendors. As manufacturing technology progresses, the OpenPDK Coalition will see significant obstacles to its work as foundries find it necessary to develop methods that are more and more proprietary due to the manufacturing requirements at 20 nm and below.

The newest project within Si2 is the Open3D Technical Advisory Board. One promising area of system integration is the use of 3D structures within a package. For an industry that has thought in two dimensions for practically its entire existence, architecting and developing a system in three dimensions presents very hard problems. Architectural design is critical, since moving blocks from one layer to another will be very expensive. The problem that the industry faces has many dimensions, and the one that Si2 has not been very effective at solving is the business side of the issue.

For reasons that are at the core of Si2, its specifications do not have the power and wide acceptance of international standards, like those of the IEEE. As a result, for example, its Common Power Format (CPF) developed by the Low Power Coalition, generated confusion and additional work in the industry when the Unified Power Format (UPF) developed by Accellera in order to free the industry from the Si2 requirements became the IEEE 1801 Standard.

Accellera became an organization in the first quarter of 2000, the result of the merger of OVI and VI. These two organizations had realized that their missions, centered respectively on Verilog and VHDL had reached the end of their missions and that the industry needed a wider approach to the problems of IC design. As a result of its recent mergerwith OSCI, Accellera has enlarged its mission to cover all aspects of system level design. In addition to its support for six IEEE standards that originated from its technical committees, Accellera has thirteen working groups and committees working on IP issues, Verification proposals that cover analog, IP, coverage measurements and of course various aspects of the SystemC community. May be surprisingly, VHDL support and extension work has remained with the IEEE, as Accellera continues to focus on both SystemVerilog and SystemC.

Both organizations perform a positive role within the industry. But their roles must be understood within the limits of each. Cadence has always played a role within Si2 that is much greater than any other consortium member, while Accellera is “managed” by Synopsys, Mentor, and Cadence who have invested staff resources to direct the consortium since its inception.

Future

Future standards development must address complexity that arises from both ends of the IC development flow. At the front end, the issues that demand attention are reuse and heterogeneity. At the back end the process of fabricating and packaging such large systems as effectively as possible to contain size, power consumption, and costs.

Although IP reuse is now common, it is still more costly and difficult than it should be. Lack of standards is the major contributor to this situation. The industry needs standards for the documentation of IP cores, that will support the design and verification of cores from multiple suppliers as well as portability across manufacturing processes. The latter may become a mute point soon as 20 nm and especially 14 nm processes become more foundry dependent. This will require that every third party IP used in these processes be guaranteed by the foundry up front.

Heterogeneity encompasses digital/analog, hardware/software, and electrical/mechanical issues. Systems will frequently have to handle all three at the same time requiring very careful architecting of the system. Although a few tools are becoming available, much work still needs to take place. Just as an example, after years of discussions and work, we still do not have a strong, reliable standard for analog/mixed signal design or verification language. And this with a problem that is totally within the control of our own industry!

The industry has made some progress in the area of hardware/software integration and verification. The most used standard in this area is TLM, developed jointly by OSCI and Accellera, then still separate entities. But almost nothing is available for hardware/software co-design that would allow engineers to explore at the architectural level the implications of moving functional blocks from hardware to software and vice versa.

Surprisingly not much is talk about in EDA circles about electro/mechanical integration. This is spite of the fact that MEMS have been around for quite a few years, and that aerospace, automotive, and even consumer markets use MEMS extensively. What is available relegates MEMS to the analog domain but very little is done in the area of system level simulation and verification.

In the manufacturing and packaging area, very large SoC present two different, yet related problems. One has to do with size. Is it reliable and cost effective to try to package the entire system on one die? If not how can the system be partitioned and packaged? In addition there are issues with respect to the best process technology to use with different parts of the system. Memories, for example, could be fabricated with a more advanced process than digital logic, ensuring an overall better yield. And analog generally is not well suited to the most advanced processes, yet it should not be the determining factor when picking a process. The area of 3D packaging will certainly see significant development in the next two or three years, but standard development should proceed in parallel, or single source tools will slow progress.

One factor that complicates the development of standard is that the industry is no longer US centric. Developing countries, like China and India, will play a significant role in the development of standard. if not, we will no longer have world-wide standards, but the industry will find itself facing local standards regulating large, significant markets. this will increase the cost of developing, marketing, and supporting electronic products.

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