Gabe's EDA Update
In June 2012 Gabe Moretti will celebrate 44 years in EDA. Gabe has contributed to the industry first as a developer, then as a senior manager and now as an editor and industry observer. He is a Senior member of the IEEE and the recipient of the IEEE RonWaxman Meritorious Award. Gabe has worked … More »
IP Business; VIP for NVM; Here comes the VIPER
March 26th, 2012 by Gabe Moretti
In January of 2011 I began the publication of a newsletter “Assembling the Future”. With its March 2012 issue all readers of EDACafe can now access the newsletter for free. Each month I will write a blog that describes the contents of that particular edition. Just follow the link provided by EDACafe. If you lose it then use this one: http://www.gabeoneda.com/newsletter.
This month’s topic is Intellectual Property (IP) and its necessary companion verification IP (VIP). The first article written by Josh Lee of Uniquify presents a short history of the IP business, from its wild west origins to the still developing present days. The second article, by David Hsu of Kilopass describes the relative large VIP package necessary to verify non-volatile memory (NVM) had macro IP. Finally Neill Mullinger of Synopsys introduces the company’s new VIP family based on the VIPER architecture.
Next month’s topic is EDA standards. How they are developed, why we need them, and what is on the horizon. To contribute an article contact me at email@example.com.
A few thoughts about IP
The IP market needs not just IP cores, but also VIP functions and procedures, a way to find products, and standard procedures both commercial and technical.
The beginning of the IP market practically coincides with the commercial availability of logic synthesis. In the late eighties and early nineties, Synopsys introduced a package of synthesizable basic logic modules called Designware while at the same time HDL Systems also started selling synthesizable cores written in both Verilog and VHDL. HDL Systems later was assimilated by Philips semiconductors, victim of managerial incompetence. But Synopsys persisted and leveraging its large installed base of Design Compiler grew its IP business to a very lucrative and growing business. Its latest offering is based on the VIPER architecture described in this month’s issue of the newsletter.
Denali, now part of Cadence, was the pioneer of the VIP business. When Sanjay Srivastava started the company no one paid much attention: there was nothing “sexy” about memories. But no system can exists without memory and interface protocols continued, and continue, to evolve to more complex systems. Testing the correct functioning of the system became expensive, and Denali’s business grew and grew creating credibility for other companies to find funding in the VIP market. One of such examples of memory VIP is described in the article by Kilopass in the newsletter.
But there are more parts of the IP market that are either not well covered in the press or are not thought of as being “IP” per se. I am referring to the embedded software market. At a time when we have reached the realization that software and hardware are to be considered equally in architecting a system, embedded software remains a market in its own. But it is really IP that must have its own VIP to be of commercial quality.
I find it peculiar that the IP market and the embedded market are not learning from each other and establish commercial protocols and engineering practices that gain from both experiences. It is high time to stop thinking about computers and programs, or APPS as application programs are now called and start to think of systems.
Although in addition to Cadence, Mentor, and Synopsys there are some large sources of IP like ARM, Xilinx, Altera, and MIPS for example, there are also many smaller vendors. A designer does not always have either the knowledge or the time to find the IP core that would best fit his requirements. A service like that offered by ChipEstimate, now part of Cadence, is a solution. Although ChipEstimate sells its own products that ease the evaluation of IP cores and the integration of cores in a design, they also provide a free catalogue of IP that is believed, of course they cannot guarantee it, to be of commercial grade.
Finally the market needs standards. A few exists, like the IEEE 1685 IP-XACT, but more are needed. The march of semiconductor manufacturing technology continues and with it come more and more stringent design rules that are approximating the limit of second sourcing and porting a design to a different foundry. Foundry specific IP and VIP is approaching and with it a possible revolution in the market. yet I find very few indications that any one is seriously considering how to enable and support this transition. The market seems in denial hoping that business as usual can continue in spite of technology’s requirements. If we do not act now to prepare for the general use of IP at 20nm and 14 nm we will witness a significant slow down in the transition to those processes with grave financial consequences not just for the electronics industry but for the world economy. Let’s not forget that without electronics products, nothing gets done anymore.