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Archive for March, 2012

IP Business; VIP for NVM; Here comes the VIPER

Monday, March 26th, 2012

In January of 2011 I began the publication of a newsletter “Assembling the Future”.  With its March 2012 issue all readers of EDACafe can now access the newsletter for free.  Each month I will write a blog that describes the contents of that particular edition.  Just follow the link provided by EDACafe.  If you lose it then use this one:

This month’s topic is Intellectual Property (IP) and its necessary companion verification IP (VIP).   The first article written by Josh Lee of Uniquify presents a short history of the IP business, from its wild west origins to the still developing present days.  The second article, by David Hsu of Kilopass describes the relative large VIP package necessary to verify non-volatile memory (NVM) had macro IP.  Finally Neill Mullinger of Synopsys introduces the company’s new VIP family based on the VIPER architecture.

Next month’s topic is EDA standards.  How they are developed, why we need them, and what is on the horizon.  To contribute an article contact me at

A few thoughts about IP

The IP market needs not just IP cores, but also VIP functions and procedures, a way to find products, and standard procedures both commercial and technical.

The beginning of the IP market practically coincides with the commercial availability of logic synthesis.  In the late eighties and early nineties, Synopsys introduced a package of synthesizable basic logic modules called Designware while at the same time HDL Systems also started selling synthesizable cores written in both Verilog and VHDL.  HDL Systems later was assimilated by Philips semiconductors, victim of managerial incompetence.  But Synopsys persisted and leveraging its large installed base of Design Compiler grew its IP business to a very lucrative and growing business.  Its latest offering is based on the VIPER architecture described in this month’s issue of the newsletter. (more…)

DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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