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A Practical Approach to Chip-level Assertion-Based Verification

Monday, October 1st, 2012

Are you using assertions in your logic verification?

Assertion-based verification is rapidly gaining popularity as a methodology for more efficient SoC debugging. Both HDL simulators and property-based formal verification tools are recognized as assertion-based verification platforms.

However, since the execution speed of an HDL simulator decreases drastically with increasing design size, no one recommends deploying an HDL simulator for chip-level verification when the full chip is hundreds of million ASIC gates or more. With formal verification tools, if the design under test (DUT) is small enough, there would be a large number of “reachable” assertions, making assertion-based verification efficient to use. However, most assertions become “unreachable” if the design size increases because logic cones in the design will become much deeper.

Consequently, neither HDL simulators nor formal verification tools are suitable as assertion-based verification platforms for full chip-level verification of large designs.


Going Against the Big Boys –– Life in EDA

Tuesday, September 18th, 2012

Everyone loves a good underdog story. In EDA, that covers about 98% of the suppliers. There are lots of them. In an industry in which three companies with broad product lines control the vast majority of the revenue, about 200 other companies, with point tools principally, battle the giants head-to-head in their own narrow product space.

Many of the smaller companies with great products and teams behind them manage to carve out a strong position with point tools. With focused resources and dedication, and a make-the-customer-successful-or-die attitude, small EDA companies are able to win, sustain themselves and, in many instances, thrive. The key is a winning strategy, whether a more focused effort on products or specialized support resources or a completely new approach to solving a customer problem.


Supporting the Community

Wednesday, September 5th, 2012

EVE has been working in partnership with the high-tech community from Austin, Texas, for a number of years now. One recent example of our community outreach is the Door64 event we sponsored in mid July at the Six Lounge in downtown Austin. More than 160 members of Door64 registered to attend.

A diverse group of technology professionals stopped by, with discussions ranging from design and verification to other topics. We saw attendees from Freescale, IBM, AMD, Oracle and others. Also, there were individuals interested in employment with backgrounds in design, verification, sales and marketing.

The event included an open exchange among attendees while they enjoyed drinks and pizza. We offered a slide show presentation with an overview of our technology. At the end of the event, we held a drawing for an Apple iPad won by Gang Chen of Langcore Laboratory in Cedar Park, Texas.


Results from DAC Survey

Monday, August 27th, 2012

The EVE Marketing Department takes the opportunity during each live event where we exhibit, such as DAC, to survey attendees who stop by to see us. This year’s DAC was no exception and we were pleased with the number of attendees willing to take time to answer our questions.

Most of the DAC attendees we met were from the U.S., though there was a healthy number of international visitors to our booth as well. When asked their job function, most answered “designer” or simply “engineer.” Other job functions included EDA tool support, management, verification/validation specialist or system architect. In other words, DAC had a wide range of attendees, many of whom appeared to be interested in reining in their verification challenges.

On the design side of things, there was no real surprise –– Verilog was by far the most common HDL language, followed, in order of preference, by SystemVerilog, VHDL and SystemC. Perhaps a bit more surprisingly: VHDL beat out Verilog, SystemVerilog and SystemC, in that order, for testbenches.


Hardware-Assisted Verification Platforms for Verifying Video and Graphics Chips

Wednesday, August 1st, 2012

Hardware-assisted verification platforms have been proven to support the verification needs of modern SoC realization. These platforms offer multi-MHz performance and comprehensive hardware debugging capabilities, which enable pre-silicon hardware/software co-verification and software validation.

However, each ASIC/SoC application also has its own unique challenges and requirements, and supporting their needs requires more than just fast emulation and 100% design accessibility. SoC realization also requires a high-performance, system-level verification platform surrounding the emulated design, including many application-specific peripherals and interfaces.

In this recurring blog series, we will explore specific SoC applications, assessing the design challenges and benefits of hardware-assisted verification, and examining the protocols and IP required to support SoC development.


SoC Verification Made Easy

Tuesday, July 10th, 2012

Yes, you read the headline correctly and there are no typos in it. For 10 years or more, companies such as EVE have focused their engineering resources on providing high-performance, application-specific validation solutions with the goal to simplify the process of verifying complex SoC designs.

Yes, again –– A tall order, but not impossible, even as the International Technology Roadmap for Semiconductors (ITRS) reports that the number of processors and the amount of software will double with each semiconductor technology node. This increasing level of SoC complexity demands more feature-rich solutions for hardware and software verification to keep project schedules and resources within reasonable bounds.

And verification providers should comply. The goal, then, is for hardware-assisted verification companies to provide an ecosystem of application-specific, system-level validation tools around their SoC emulation systems that cover the broad spectrum of functions built into complex SoC designs. The key is to build each platform in a way that simplifies the effort of the project design and verification team to setup, run and then debug complex designs. The platforms must also leverage all of the advanced debug facilities in the emulation system.


EVE’s Positive Impressions of This Year’s DAC

Tuesday, June 19th, 2012

DAC may be over, but the feeling of community and a job well done has stayed with those of us who staffed the EVE booth. We are quite happy with the turnout this year and, if you walked by our booth, you’ll know why –– our presentations were well attended all three days. Monday, in particular, was brimming with attendees all eager to learn more about our ZeBu hardware-assisted verification platform. In fact, we scheduled an additional presentation or two due to the heavy traffic and high degree of interest.

ZeBu’s new Post-run Debug (PRD) capability, a way to ensure that verification engineers never miss capturing a bug, created a lot of excitement, as did our low-power verification to check functional integrity of multi-power domains or islands on/off switching. They were complemented by our ESL co-emulation for early software development. New and updated application-specific debug environments for wireless handsets, Ethernet and HDMI video generated loads of notice as well.

For EVE, DAC is an opportunity to connect with the community. We treat it as a way to get in front of a large number of community members, including existing customers, prospects, partners and competitors, in a short amount of time. We were able to schedule important meetings. It’s an opportunity to demonstrate ZeBu and create a positive first impression of EVE. While we enjoy ourselves at DAC, we work hard, but it is well worth the effort, especially since we set specific, measurable goals to succeed.


Evaluating a Transaction-Based Co-Emulation Methodology

Friday, June 1st, 2012



Note:I’m turning over today’s blog to Takashi Kawabe of Konica Minolta and my colleague Mitsuhiro Matsumoto of EVE KK who will describe how Konica Minolta evaluated and selected EVE’s ZeBu. Kawabe-san will present more details during the DAC User Track Thursday, June 7, from 9-10:30 a.m. at the Moscone Center, Room 303.

Konica Minolta Technology Center, Inc., of Tokyo, Japan, is known for its high-speed, high-performance LSI designs used in image processing. As most semiconductor companies can attest, it is finding that the hardware debugging process is getting more and more complicated.



Tuesday, May 22nd, 2012

DAC is only a few short weeks away. At EVE, we’re busy finalizing our demos and presentations, and getting ready to ship our booth to the Moscone Center in San Francisco.

It’s an exciting time for us and we look forward to seeing attendees and fellow exhibitors again this year. Our attention will be focused on why so many companies are turning to EVE for their complex SoC verification needs.

For example, we see increasingly strong demand for our ZeBu SoC emulation, the leading solution for accelerated transaction-based verification. In the last two years, more than 30 design teams adopted the new ZeBu-Server for validating very complex SoCs.

Among them are:

  • Texas Instruments confirmed recently that it used ZeBu-Server to accelerate development of its embedded software for the OMAP 5 platform –– a big deal for us and a huge win for software developers.
  • Fujitsu Microelectronics Solutions Limited in Japan announced last week that it adopted ZeBu and ZEMI-3 transaction-level modeling methodology to use within its integrated algorithmic C verification RTL emulation flow to complete a high-level synthesis design methodology.
  • Konica-Minolta will offer a look at how it uses ZeBu in a User Track scheduled for Thursday, June 7, from 9-10:30 a.m. in Room #303.

Moreover, we just closed our fiscal year with more than $60 million in bookings.


Emulation Evolved, Part 2

Monday, May 7th, 2012

In my previous blog post, I began an exploration of the evolution of emulation. Indeed, over the years emulation has evolved into a mandatory component of the SoC realization process, offering multi-MHz performance, improved time-to-emulation, and simulator-like debugging capabilities—all in a compact, low-power chassis.

But emulation providers like EVE don’t have time to rest on our laurels. The challenges of SoC design and verification are continuously changing, and it’s not enough for us to simply keep pace—we need to account for future developments as well. Accounting for future evolution in emulation requires both scalability and continued innovation.


S2C: FPGA Base prototyping- Download white paper

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