Matsumoto joined EVE KK in 2008 and is working as AE manager. He started his career at Texas Instruments Tsukuba Research and Development Center in 1996. His technical expertise covers hardware-assisted verification, assertion-based verification and Universal Verification Methodology (UVM).
A Practical Approach to Chip-level Assertion-Based Verification
October 1st, 2012 by Mitsuhiro Matsumoto
Are you using assertions in your logic verification?
Assertion-based verification is rapidly gaining popularity as a methodology for more efficient SoC debugging. Both HDL simulators and property-based formal verification tools are recognized as assertion-based verification platforms.
However, since the execution speed of an HDL simulator decreases drastically with increasing design size, no one recommends deploying an HDL simulator for chip-level verification when the full chip is hundreds of million ASIC gates or more. With formal verification tools, if the design under test (DUT) is small enough, there would be a large number of “reachable” assertions, making assertion-based verification efficient to use. However, most assertions become “unreachable” if the design size increases because logic cones in the design will become much deeper.
Consequently, neither HDL simulators nor formal verification tools are suitable as assertion-based verification platforms for full chip-level verification of large designs.
Logic emulation systems –– in particular, EVE’s fast SoC emulator ZeBu –– are able to overcome capacity and performance issues in chip-level assertion-based verification for large SoC designs. Emulation systems provide fast, megahertz execution speed regardless of the design size. This benefit is an attractive reason why design teams are adopting the assertion-based verification with emulators.
When a logic emulation system is deployed, assertions are synthesized and mapped into FPGAs together with the DUT logic by the system’s compiler. Once an assertion-based verification environment is set up with an emulator, you can execute the design with the embedded assertions via real long streams of data, such as a 2K/4K video and executing actual embedded software like the Android OS.
Assertions in an emulation environment track coverage, validate design intent and can initiate or trigger activity in the verification environment –– all beneficial impacts on the verification process.
Because of these benefits, logic verification engineers increasingly are interested in the assertion-based verification with emulation systems. Recently, a design team applied this methodology, emulating their design, testbench and assertions using ZeBu. They discovered one of the outstanding benefits of the ZeBu assertion-based verification environment –– there was no performance overhead due to the assertions; ZeBu maintained its industry-leading performance.
Results also showed that ZeBu assertion-based verification users should take care in writing the assertions to be applied in emulation, and to consider hardware resource consumption due to the assertions. An assertion consumes some logic resources in the emulator. The amount of resources consumed depends on the contents and the coding style of the assertions. This can impact the size and compile time of the synthesized netlist.
Results have been announced in the following news release: http://www.eve-team.com/news/2011/November_3__EVEs_ZeBu_Hardware-Assisted_Verification_Platform_Used_by_Konica_Minolta_to_Implement_SystemVerilog_Assertions.html
Through the user’s real experience described above, the ZeBu assertion-based verification methodology opens the door to a new world of assertion-based verification.
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