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Archive for October, 2012

A Practical Approach to Chip-level Assertion-Based Verification

Monday, October 1st, 2012

Are you using assertions in your logic verification?

Assertion-based verification is rapidly gaining popularity as a methodology for more efficient SoC debugging. Both HDL simulators and property-based formal verification tools are recognized as assertion-based verification platforms.

However, since the execution speed of an HDL simulator decreases drastically with increasing design size, no one recommends deploying an HDL simulator for chip-level verification when the full chip is hundreds of million ASIC gates or more. With formal verification tools, if the design under test (DUT) is small enough, there would be a large number of “reachable” assertions, making assertion-based verification efficient to use. However, most assertions become “unreachable” if the design size increases because logic cones in the design will become much deeper.

Consequently, neither HDL simulators nor formal verification tools are suitable as assertion-based verification platforms for full chip-level verification of large designs.


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