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Lauro Rizzatti - General Manager, EVE-USA
Lauro Rizzatti - General Manager, EVE-USA
Lauro is general manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing and engineering.

Hardware-Assisted Verification Platforms for Verifying Video and Graphics Chips

August 1st, 2012 by Lauro Rizzatti - General Manager, EVE-USA

Hardware-assisted verification platforms have been proven to support the verification needs of modern SoC realization. These platforms offer multi-MHz performance and comprehensive hardware debugging capabilities, which enable pre-silicon hardware/software co-verification and software validation.

However, each ASIC/SoC application also has its own unique challenges and requirements, and supporting their needs requires more than just fast emulation and 100% design accessibility. SoC realization also requires a high-performance, system-level verification platform surrounding the emulated design, including many application-specific peripherals and interfaces.

In this recurring blog series, we will explore specific SoC applications, assessing the design challenges and benefits of hardware-assisted verification, and examining the protocols and IP required to support SoC development.

In this blog, we’ll look at how designers of video and graphics processing chips can benefit from hardware-assisted verification. Video processing for HDTV and encoding/decoding (e.g., H.264, MPEG.4) functionality has proliferated into a wide range of market segments that include networking, home entertainment and broadcasting and data communications, as well as security and surveillance.

Verifying video and graphics functionality in chips or large IP blocks always presents challenges due to the sheer amount of cycles required to run any significant images through the design. With the advent of high-definition TV in particular, the amount of data handled by the device has dramatically increased, making traditional simulation of full-size HDTV frames impractical.

One 1920x1080p HDTV frame typically requires several million cycles of simulation. At 60Hz, one second of real-time video requires 400 million cycles that could take weeks or even months to simulate. As a result, designers have resorted to all kinds of tricks to shorten the simulation time, like scaling down the frame size or running single frames separately.

Ultimately, these changes mean that verification of SoC is no longer representative of the real-world—in order to verify the design at the application level, a designer needs to run full-size frames serially. This is where hardware-assisted verification like ZeBu comes into play.

Hardware-assisted verification gives hardware designers the ability to verify video data in frames per second instead of frames per hour or per day. At these rates, a designer can process real-world video, transcode long bitstreams, and actually interact with the rest of the system, be it a PC, or simply a DVI or HDMI display.

How does one build this system-level environment?

ZeBu users are able to leverage an e-zTest suite of application specific validation platforms to quickly build a system-level test environment for emulation. For multimedia applications, DVI and HDMI output can be virtualized through Digital Video and HDMI sink e-zTest platforms. PCI-Express Gen1/2/3 e-zTest platforms enable the integration of a graphics device with a virtualized Windows or Linux PC for driver development and software validation. Software development is further enabled through virtual JTAG connectivity, providing integration with common software debuggers. Standard DDR2, LPDDR2, and GDDR5 memory models, implemented in the ZeBu hardware, provide frames buffers and system memory.

In one recent application, ZeBu was used to verify the picture-in-picture (PIP) and de-interlacing functionality of an HDTV video processor. Two high-definition video sequences were streamed to the design mapped in ZeBu. The resulting PIP video was streamed out and virtualized on the host PC. By achieving multiple megahertz in emulation speed, the system generated a frame every few seconds that made it easy to verify long video sequences, and the virtualized display made it possible to visually ensure that no invalid video artifacts were generated by the chip.

With their long verification sequences and system-level integration and virtualization requirements, video and graphics SoCs are ideal candidates for hardware-assisted verification platforms like ZeBu, complemented by e-zTest IP.

This is just one potential application. In future posts, we will discuss platform requirements of other applications, ranging from processors, wireless communications, ESL, storage, networking and automotive.

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