The EVE Marketing Department takes the opportunity during each live event where we exhibit, such as DAC, to survey attendees who stop by to see us. This year’s DAC was no exception and we were pleased with the number of attendees willing to take time to answer our questions.
Most of the DAC attendees we met were from the U.S., though there was a healthy number of international visitors to our booth as well. When asked their job function, most answered “designer” or simply “engineer.” Other job functions included EDA tool support, management, verification/validation specialist or system architect. In other words, DAC had a wide range of attendees, many of whom appeared to be interested in reining in their verification challenges.
On the design side of things, there was no real surprise –– Verilog was by far the most common HDL language, followed, in order of preference, by SystemVerilog, VHDL and SystemC. Perhaps a bit more surprisingly: VHDL beat out Verilog, SystemVerilog and SystemC, in that order, for testbenches.