The EVE Marketing Department takes the opportunity during each live event where we exhibit, such as DAC, to survey attendees who stop by to see us. This year’s DAC was no exception and we were pleased with the number of attendees willing to take time to answer our questions.

Most of the DAC attendees we met were from the U.S., though there was a healthy number of international visitors to our booth as well. When asked their job function, most answered “designer” or simply “engineer.” Other job functions included EDA tool support, management, verification/validation specialist or system architect. In other words, DAC had a wide range of attendees, many of whom appeared to be interested in reining in their verification challenges.

On the design side of things, there was no real surprise –– Verilog was by far the most common HDL language, followed, in order of preference, by SystemVerilog, VHDL and SystemC. Perhaps a bit more surprisingly: VHDL beat out Verilog, SystemVerilog and SystemC, in that order, for testbenches.

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Hardware-assisted verification platforms have been proven to support the verification needs of modern SoC realization. These platforms offer multi-MHz performance and comprehensive hardware debugging capabilities, which enable pre-silicon hardware/software co-verification and software validation.

However, each ASIC/SoC application also has its own unique challenges and requirements, and supporting their needs requires more than just fast emulation and 100% design accessibility. SoC realization also requires a high-performance, system-level verification platform surrounding the emulated design, including many application-specific peripherals and interfaces.

In this recurring blog series, we will explore specific SoC applications, assessing the design challenges and benefits of hardware-assisted verification, and examining the protocols and IP required to support SoC development.

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