Lauro Rizzatti - General Manager, EVE-USA
Lauro is general manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing and engineering.
May 1st, 2012 by Lauro Rizzatti - General Manager, EVE-USA
DAC’s coming and, at EVE, we’re thinking about the evolution of emulation, a theme that you’ll hear more about from us. It’s been fascinating to look at how emulation has evolved from high-priced, hard-to-use clunkers introduced in the 1980s to sleek, low-cost hardware-assisted verification solutions that execute at high speeds.
At $1 million per seat, those early emulators were available to only the largest companies doing the most complicated designs. Cost alone prevented widespread deployment, and they quickly became outdated as new process technologies emerged, quashing their practicality and curbing accuracy. The maximum speed was about one MHz, slow even then, and they were roundly criticized for being difficult to set up. The designer’s lament was the excessive time to emulation.
Even the purveyor of the traditional, high-end hardware emulators knew these machines needed a serious overhaul. An executive from one the big three EDA vendors once said, “An emulator you used four years ago, you can use as a bookend, but not much else. Or, you can throw it over the side of a boat and use it to grow coral.” A great line and oh so true.
Fortunately, traditional hardware emulators have been pushed aside by hardware-assisted verification platforms designed and implemented with the largest and newest commercially available FPGAs.
The evolution began around 2000 –– the new millennium, as we said back then ––when it became apparent that hardware-assisted verification and embedded software validation needed to be done concurrently. With software as a product differentiator, emulation often is used for hardware/software co-verification because designers implementing SoCs must be able to verify the correctness of both hardware and embedded software. Hardware designers and software developers at last can share the same system and design representations, reducing software development time ahead of silicon.
The new wave of hardware-assisted verification platforms execute at a higher speed –– several megahertz. That’s mandatory, in fact, to boot an RTOS such as Android in a few short minutes –– than traditional emulation systems, offering the same design debug environment at a lower cost and packaged in a small footprint. With more than a billion ASIC-equivalent gate capacity, these emulators are easy to learn and easy to set up.
What’s more, they can cut time to tapeout, improve product quality and eliminate re-spins. They have a small footprint and are light weight, saving space, power and infrastructure costs. Their debugging capabilities are similar to an HDL simulator, and increasingly are used as a solution to an event-based simulator’s runtime problems.
Yes, there’s been evolution in emulation and it doesn’t end here. In our next installment, we’ll look to the future and what designers can expect from even newer hardware-assisted verification solutions.
Until then, a bientot … or see you later!