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Archive for January, 2012

EVE’s Events Season Gets Underway

Tuesday, January 24th, 2012

It’s only January, but EVE’s event calendar for the first half of 2012 is filling quickly. We kicked off the year with a presentation by Luc Burgun, EVE’s president and CEO, at the 14th Annual Needham Growth Stock Conference January 10. This was the first time we were invited to participate and we were delighted. From all accounts, his presentation was well received.

Next up is DesignCon January 31-February 1 at the Santa Clara Convention Center in Santa Clara, Calif. We’ll be in Booth #721 from 12:30-6 p.m.

We move on to Shenzhen, China, for IIC China Conference and Exhibition February 23-25, where we will be in Booth #1L26.

Local Silicon Valley favorite DVCon returns to the Doubletree Hotel in San Jose in late February. EVE will exhibit February 28-29 in Booth #602.

Luc Burgun will represent EVE at a panel during DATE March 12-16 in Dresden, Germany. The panel, “Accelerators and emulators: Can they become the platform of choice for hardware verification?,” will be held and will be held Wednesday, March 14, at 8:30 a.m. It will be moderated by Professor Bashir M Al-Hashimi from the University of Southampton.

SNUG Silicon Valley at the Santa Clara Convention Center will host a Designer Community Expo March 26-28 and EVE will be there as a Synopsys partner.

The first half of the year culminates with DAC, as it always does for the designer and EDA community, and EVE will be there in Booth #1926. We’ll have more details about our plans for DAC in the coming months.

Please introduce yourself to any of the EVE staff member at the events we’re attending to learn more about us and our hardware-assisted verification products. At each, you will have an opportunity to discover ZeBu-Blade2, the first member of the ZeBu emulation family based on Xilinx Virtex6-LX760 FPGAs, used for ASIC and SoC designs implemented in 40-nanometer technology. It offers fast execution and attractive pricing for best-in-class hardware/software integration ahead of silicon availability.

And, do stay tuned for more on what we’re doing in the second half of 2012.

Pondering the Next Big Idea

Monday, January 9th, 2012

Not long ago, I overheard a thought-provoking exchange related to the demise of a beloved cultural icon. This conversation gave me pause to consider what intriguing new application is coming next that will displace another symbol of popular culture, much like what’s happened to local book and video stores or hard-wired landline phones. I’m sure some clever entrepreneur is already designing an enabling technology to open a new world for us, beyond our current habits. Gone may be a beloved local store or pink Princess phones, but consider the access to a variety of new adventures offered by these future innovations.

Ah, but these game-changing technologies don’t exist in a vacuum. They rely on innovations occurring at all levels of development. The next iconic technology will require more than just sophisticated application software and fast internet connections. It will also require a robust infrastructure able to crunch through and process, compress, and transport the massive amounts of data. That infrastructure will be built on the next generation of multicore (or manycore) SoC devices executing previously unimaginable amounts of embedded software. And these SoC devices will in turn be designed and verified using the latest and greatest EDA technologies, most notably, emulation.

To support the next big idea, every EDA tool requires innovation, but this is especially true for emulation, given its growing prominence in the process of SoC realization. As I’ve written in the past, emulation has become mandatory for the verification of complex chips. Thus, emulators can’t just keep up with the requirements of SoC development; they must outpace them. SoC design sizes of 20- or 30-million gates are common today, but the emulator for tomorrow must be able to cross the billion-gate threshold. Similarly, the 500kHz to 1MHz performance that emulators have traditionally supplied simply won’t cut it for next-generation SoC designs. You need an order of magnitude performance boost if you are going to boot an OS, transcode high-definition video, or process multiple pages of scanned images.

Innovation isn’t always about size or speed. Sometimes it’s about breaking down barriers and improving accessibility. Design teams around the globe have concluded that an emulator can accelerate the verification process across the entire SoC project. To support this surge in adoption, emulators must evolve into a cost-effective and flexible solution that supports both enterprise- and desktop-level usage.

I’m still pondering what the next big idea will be, all-the-while knowing that innovations in emulation will play an important supporting role. I welcome your thoughts.

ClioSoft at DAC
TrueCircuits: IoTPLL

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