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Archive for September, 2014


Monday, September 29th, 2014

Todays SOC designs are architected top-down and designed bottom-up, meaning that the design specifications are dictated from the top level requirements and budgeted downwards to lower level blocks. Once lower level blocks are designed and completed the resulting block level characteristics are integrated upwards, or bottom-up for final SOC assembly.

Much attention has been devoted to functional aspect of the top-down to bottom-up design approach. Many tools are available in designers’ arsenal to validate the functional aspect of the design from simulators, linters, to formal equivalency checkers, etc. As a result functional design specification are propagated to lower level blocks and once block level design is complete, the performance metrics are propagated back to the top for functional validation. Such metrics however are missing when it comes to timing data, which for the most part are ignored from the functional simulation and it is left to the designer to “later” specify and capture them in the form of timing constraints. The process of the timing constraints definition as well as downward or upward propagation of such information is basically manual and solely relies on designer memory, skill, and intelligence with little automation aid to help in validating the information once captured.


ClioSoft at DAC
TrueCircuits: IoTPLL

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