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Rick Eram, Sales & Marketing VP
Rick Eram, Sales & Marketing VP
Rick has over 20 years of hands on experience in EDA industry, designing tools and directly involved in development and management of engineering teams as well as managing sales and marketing campaigns. Rick's work was instrumental in 2 IPO's with Analogy and Magma. During his tenure at Atrenta he … More »

Value of timing constraints files beyond STA

 
December 10th, 2014 by Rick Eram, Sales & Marketing VP

Timing Constraint files are one of the best timing and clock data containers available to the designers, yet they are under utilized today and their value is not fully exploited in the design flow.

The timing information captured in timing constraints files often hold very valuable timing and clocking information. This valuable source of timing data can help the design teams to shorten the design cycles, improve verification quality, and increase analysis accuracy by providing timing information from early design stages to many downstream tools saving valuable time trying to extract timing information manually. The timing and clocking information can not only improve analysis capability and accuracy of downstream tools, but also save a great deal of unnecessary manual setup process which invariably reduces the verification burden and expands the coverage of any such verification work by allowing automated setup of static verification tools such as various flavors of linting tools.

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CHALLENGES PROPAGATING TIMING INFORMATION

 
September 29th, 2014 by Rick Eram, Sales & Marketing VP

Todays SOC designs are architected top-down and designed bottom-up, meaning that the design specifications are dictated from the top level requirements and budgeted downwards to lower level blocks. Once lower level blocks are designed and completed the resulting block level characteristics are integrated upwards, or bottom-up for final SOC assembly.

Much attention has been devoted to functional aspect of the top-down to bottom-up design approach. Many tools are available in designers’ arsenal to validate the functional aspect of the design from simulators, linters, to formal equivalency checkers, etc. As a result functional design specification are propagated to lower level blocks and once block level design is complete, the performance metrics are propagated back to the top for functional validation. Such metrics however are missing when it comes to timing data, which for the most part are ignored from the functional simulation and it is left to the designer to “later” specify and capture them in the form of timing constraints. The process of the timing constraints definition as well as downward or upward propagation of such information is basically manual and solely relies on designer memory, skill, and intelligence with little automation aid to help in validating the information once captured.

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