Dr. Russ Henke
The writer of the following article has posted over 100 articles on EDACafe.com since 2003, in the form of Quarterly Commentaries on the worldwide EDA and EDA IP Industries as well as monthly Editorials covering vendors, products, finances and new developments. Beginning April 2012 these … More »
Silicon Valley: EDA Magnet! – Part II
February 19th, 2012 by Dr. Russ Henke
Introduction to this February 19, 2012 Blog Entry
This writer’s very first BLOG entry ever, initially posted on February 7, 2012, is still visible to readers in the sea of words below. In case you wish to refer to it, the beginning of that blog entry looks like this:
February 7th, 2012 by Dr. Russ Henke
This initial blog entry of February 07 may have looked familiar. That’s because it was copied directly from the EDA WEEKLY of February 06, 2012, the 31st in a series posted in EDACafe.com every four weeks or so by this writer since November 2009.
These identical articles contain profiles of two particular EDA enterprises (Silicon Frontline, Campbell CA & Breker Verification Systems, Fremont CA) drawn to the Silicon Valley by the “magnetic attraction” of this locale.
Alas, space limitations and deadlines for the first profiles caused the profile on Breker to be foreshortened. The remainder of the Breker article describing Breker technology, was to be posted in the subsequent EDA WEEKLY scheduled for March 05, 2012.
But since Breker will be at the DVcon Design & Verification Conference & Exhibition at the Doubletree Hotel in San Jose February 27 – March 01,
we decided to accelerate the posting of the missing Part II piece of the Breker profile in today’s BLOG column.
A New Methodology from Breker to Solve Verification Problems
“The EDA industry has focused on block-level verification,” says Dr. Adnan Hamid, Breker co-founder and CEO, as he sets the stage to describe further, why Breker Verification Systems came into being. “Previous languages and methodologies have been developed that enable tests to be automatically created from a unified testbench description, but these (previous) approaches don’t scale or adequately address system-level verification,” asserts Adnan.
“When multiple processors and many different types of IP are involved, methodologies in use for block-level verification break down.” By studying the way that the EDA Verification segment has arbitrarily evolved, i.e. without the guidance of a real strategic focus, Adnan came to believe that a new verification methodology was essential.
This methodology should begin with the end in mind. That is, embrace the verification goal to be defined and include an automated tool that will find a valid way of achieving that goal. This methodology must also be able to handle one or more processors within the system and be able to coordinate multiple concurrent activities within the system. It should be able to handle all integration verification tasks as well.
The only way to solve this problem, he concluded, was to stop focusing on stimulus and instead think about “goals and outcomes.” Tools should be constructed that can find ways to meet goals and to be able to provide a sample of the possible ways those goals can be achieved using different parts or paths through the system.
Enter SoC verification and breaking verification icebergs –– foreign jargon or new buzzwords to many, but the concept won’t be. The rapid growth of SoCs is driving a fundamental paradigm shift in verification, due to the extensive use of embedded processors. SoC verification is a complex task that includes thorough verification of the system and IP interconnect, shared system resources, use cases and system performance.
Constrained, random test pattern generation was once hailed as a great advance over “directed testing,” the previous mainstay of functional verification, according to Adnan. The arrival of SystemVerilog and UVM tools, now well-integrated into the design flow, enable transactional tests to be automatically created from a unified testbench description for IP block-level verification. While their suppliers claim to fix the verification problem, Adnan says that many of these so-called advancements are limited in their capabilities and “delay the inevitable.” According to Adnan, functional verification has become the congestion point for many designs.
“One of the biggest flaws of current methodologies is to rely on hope as a strategy,” he continues, “Or verifying the independent IP and stitching them together, hoping that the SoC will work as intended. Testing an SoC that uses embedded processors, requires additional software tests typically written in C. And, where do these tests come from?”
Today, SoC verification engineers design and write these tests one at a time, manually, a time and labor-intensive process. Unfortunately, these tests typically only address the tip of the SoC verification “iceberg,” leaving behind system bugs that are not discovered until much later. Bugs discovered late in the development process delay time to market and affect revenue. Now that statement makes sense!
“This is where Breker’s TrekSoC comes to the rescue?,” asks the writer.
Iceberg? Trek? –– is this picture getting any clearer? Both Adnan and Maheen Hamid believe that the tools needed by verification engineers must be easy to use, modular, extensible, scalable and reusable. TrekSoC utilizes what Breker calls “SoC Scenario Models” that focus on a device’s intended outcomes and then automatically generates the stimulus required to generate those outcomes. It is used for generating constrained random C test cases to target system interactions that are self-checking and optimized to run efficiently in simulation. The same SoC Scenario Model can also be used to drive transactional test cases at the sub-system and for IP testbenches, as well as in the validation process, extending from pre-silicon to post-silicon.
OK. Hold the phone! The writer once again realizes that he is glad that long ago he chose mechanical engineering as his major!
Defining SoC Verification
Lets go back and get some fundamental definitions. SoC Verification is the ability to establish that system-level capabilities, such as functionality, performance and power management, can be shown to perform according to specification. Got it!
A system is made up of numerous IP blocks that can come from a variety of different sources, including third parties and internal design teams. Even though each individual IP block might each be verified on its own, the verification team should not assume that blocks will operate correctly when fully integrated within the SoC. Issues such as shared resources, interrupts and system management need to be considered, as well as application use cases and performance.
Now we’re getting the picture. The SoC verification problem is so daunting that it can only be solved through automation. Just consider the vast number of SoC use cases that span multiple concurrent applications with shared resources and on-board power and clocking management systems –– an overwhelming number of possible scenarios.
TrekSoC delivers the software to tackle this problem by applying automation to determine what to test and then rapidly developing the necessary tests to adequately cover the wide spectrum of verification objectives. It is the first commercially available software that automates the creation of portable self-checking tests for multi-threaded, multi-processor SoC devices. according to Breker!
It’s modular, extensible and scalable, and utilizes SoC Scenario Models that focus on a device’s intended outcomes and then automatically generates the stimulus required to generate those outcomes. It is used for generating constrained random C test cases to target system interactions that are self-checking and optimized to run efficiently in simulation. As a structured approach to SoC verification, it can be deployed incrementally with a high return on investment. Easy to use and learn, TrekSoC offers simple graph-based models with visualization and coverage analysis, along with easy reuse of verification models.
The SoC Scenario Modeling approach to functional verification handles IP-to-SoC reuse and pre-silicon to post-silicon reuse. The technology provides a simple “algebra” to describe a desired verification search space as visualized, using a combination of graphs and graph constraints. It generates input stimulus, checks results and measures coverage closure, creating transactional tests at the IP level and C tests at the SoC level. Visual analytical capabilities include interactive rendering of pre-simulation reach-ability analysis and post-simulation coverage results.
TrekSoc leverages the existing verification infrastructure. It integrates with all existing verification methodologies, including UVM, OVM and the VMM and hardware languages such as SystemVerilog and Verilog, and all commercially-available simulators.
The impact of adopting the Breker methodology goes beyond the immediate advantages of verifying the SoC’s functionality and, in fact, it can work at all stages of the design and development flow. As a result, since it can be applied to models at any level of abstraction, the verification task no longer needs to be relegated to the end of development activity as it has been in the past. Design teams with a virtual prototype created for software development can start verifying at the same time. Earlier in the flow means having the time necessary to implement the various types of verification, along with the tools to ensure that coverage goals can be met.
“Bringing integration verification earlier in the cycle allows tasks such as performance verification to have a greater impact,” affirms Adnan. “Rather than finding problems late in the development cycle, it’s possible to optimize the system for the desired performance and to ensure that the correct controls exist within each block for proper power management. In effect, integration verification becomes a design task and performing verification on abstract models enables a more efficient process with execution speeds often orders of magnitude faster than for RTL verification.”
All this may be obvious to the few skilled verification engineers around the world, and Breker identifies itself with those verification engineers. With each new design seeming more complex than the last, verification engineers are an integral part of a product’s success, believe Adnan and Maheen. With more SoC designs, there is a growing class of verification engineers that is woefully under-appreciated in terms of the complexity of the job they have to do and the lack of tools made available to them. After all, they are given the weighty responsibility for overall integration verification, system verification and validation.
While Breker’s goal is to give these verification engineers the tools to be successful, credibility comes from the words of the initial TrekSoC users now publicly proclaiming its value. Now in production use at leading semiconductor companies in the United States, Europe and India, TrekSoC is developing a loyal following of verification engineers at companies such as NVIDIA and ST Microlectronics, among others.
François Cerisier, IC verification expert at EASii IC, says, “With Breker, we can provide a higher level of verification efficiency with improved coverage closure in pre-silicon and post-silicon verification activities for our customers.”
A recent DeepChip post included a comment about Breker’s Trek SoC, written by a verification engineer: “Breker Verification Systems’ Trek tool has been refreshing. A new look at how to do functional verification. As a verification engineer, we all look at outcomes to figure out our test plan. Breker takes that to a new level where we can create graphs based on outcomes and even more power comes when one can apply a static analysis to see if all outcomes can really be reached by what was created.”
The Verification Guild, a forum where verification professionals can discuss issues and challenges, is moderated by Synopsys Fellow Janick Bergeron. It included a recent discussion about Breker’s TrekSoc that shows that TrekSoC is a highly useable tool. One respondent wrote: “Their SoC verification strategy proposal is solid and we are happy of the improvements it brings to our flow.”
Another noted: “They leverage an already existing test suite to create more stressful SoC tests.”
“Trek is so versatile,” wrote another design verification engineer about Breker’s first-generation product and the underlying technology for TrekSoC. “I was able to plug in a Trek graph that modeled the DUT in place of the actual DUT (whose RTL for some features wasn’t ready), allowing me to develop Trek graphs that would test features that weren’t even implemented yet.”
More guild members followed with: “Trek is more effective on complex designs. It really helps get to deep corner cases that aren’t easily hit.”
And this: “My first impression was to use Trek simply as a test case creation engine but slowly I’m getting convinced it is useful as ‘checker’ as well, especially the end-to-end checks.”
“Trek has a natural way of implementing a test environment with knowledge-driven approach of directed tests and the flexibility of incorporating randomness into the scenario generation and checking,” noted one final commenter.
Well, loyal readers, there you have it: The still-emerging story of Breker Verification Systems and the way to break verification icebergs, as told by Breker co-founders Adnan and Maheen Hamid, reported to the best of this writer’s ability, and with the skillful assistance of Nanette Collins.
Breker, Trek, Iceberg and SoC Verification may be new and unfamiliar terminology used to describe a challenge that EDA needs to tackle, but these tools and approaches hold the promise to meet head on the challenges facing verification engineers. If these promises are fulfilled, Breker Verifications Systems may be poised to become the breakout EDA company of 2012 and beyond, as it works to make verification engineers successful.
EDACafe readers are beginning to see much more of Breker in 2012 as Breker rolls out several announcements over the coming months. Already Breker appeared in EDA WEEKLY and in this blog in early February; posted a News Release on February 9 (see below); Maheen Hamid appeared as a guest writer in Real Intent’s Jin Zhang’s EDACafe.com blog on February 16; and as mentioned above, the Company will be at DVcon at the end of this month.
And if that’s not enough, Breker will be at DAC in San Francisco June 4-6 in Booth #2501. . See ‘em there!
The writer of both the EDA WEEKLY and the Industry Commentary Blog again thanks the leadership at Breker Verification Systems for the opportunity to post the above second and concluding portion of the original February 6, 2012 Breker article; and he especially thanks Ms. Nanette Collins for her composition and insightful assistance.
News Release Feb. 8, 2012, 11:00 a.m. EST
Breker Verification Systems Closes Year 2011 With 150% Growth
Relocates to Silicon Valley, Adds Michel Courtoy to Board of Directors
FREMONT, CA, Feb 08, 2012 (MARKETWIRE via COMTEX) — Breker Verification Systems, The SoC Verification Company, today announced that it closed calendar year 2011 with year-over-year growth of more than 150%, confirming its position as the first electronic design automation (EDA) company to solve the functional verification challenges of complex system-on-chip (SoC) designs containing embedded processors.
Additionally, Breker recently relocated its corporate headquarters from Austin, Texas, to Fremont, Calif., and added noted EDA entrepreneur and verification expert Michel Courtoy to its board of directors. TrekSoC(TM), the first commercially available software that automates the generation of self-verifying test cases for multi-threaded SoC devices, is in production use at leading semiconductor companies in the U.S., Europe, and India. The latest version of TrekSoC will begin shipping in late February. More details will be available then.
“2011 was a momentous year for Breker,” remarks Adnan Hamid, Breker Verification Systems’ co-founder and chief executive officer (CEO). “We made some strategic changes to position for rapid growth and firmly establish ourselves as The SoC Verification Company. From all calculations, these moves are paying off handsomely.” For example, Breker saw year-over-year sales growth of 150% and tripled the number of licenses in active use.
Since its founding in 2003, Breker Verifications Systems’ mission has been to improve upon existing verification technologies, especially as more and more chips become SoCs with embedded processors. Effective verification of such designs requires high-quality, self-verifying test cases running on the processors. These test cases must exercise a wide range of functional scenarios to ensure that the SoC can support the necessary concurrency, system-level and software functionality while meeting performance requirements. TrekSoC can generate these test cases automatically.
“It’s rare to work with entrepreneurs with a focused and clear idea of where the company’s going and how it’s going to get there,” says Board Member Michel Courtoy. “Breker has a long-term strategic vision that’s both impressive and sound, and a team that can implement the vision.”
About Board Member Michel Courtoy
Courtoy began his career at Intel in design engineering and software engineering. He managed product marketing for layout verification software at Cadence Design Systems. As vice president of marketing for Silicon Perspective, Courtoy created the market for silicon virtual prototyping and was a key player in its acquisition by Cadence in 2001. He served as a vice president at Cadence before becoming the CEO at Certess, leading Certess through sales growth to a successful exit by acquisition. Courtoy holds a Bachelor of Science degree in electrical engineering from University Catholique de Louvain, Belgium; a Master of Science degree in Electrical Engineering from University of California, San Diego; and an MBA from Santa Clara University in Santa Clara, Calif.
About Breker Verification Systems Breker Verification Systems is an Electronic Design Automation (EDA) software company that provides innovative solutions to solve the challenge of complex system-on-chip (SoC) functional verification. Its TrekSoC(TM) software and unique SoC scenario-modeling(TM) approach are used in production at leading semiconductor companies in the U.S., Europe and India. Founded in 2003, it is privately held and funded, and based in Silicon Valley, Calif. Breker Verification Systems corporate headquarters are located at 304 Anza St., Fremont, Calif. 94539. Telephone: (512) 415-1199. Email: email@example.com. Website: www.brekersystems.com .
TrekSoC and SoC Scenario Modeling are registered trademarks of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
About the Writer of this Blog
Since 1996, Dr. Russ Henke has been active as president of HENKE ASSOCIATES, a San Francisco Bay Area high-tech business & management consulting firm. The number of client companies served by Henke Associates during those years now numbers close to fifty. Engagement lengths have varied from a few weeks up to ten years and beyond.
During his previous corporate career, Henke operated sequentially on “both sides” of MCAE/MCAD and EDA, as a user and as a vendor. He’s a veteran corporate executive from Cincinnati Milacron (Research Scientist – Oakley, OH), SDRC (President & COO – Fairfax, OH & Milford, OH), Schlumberger Applicon (Executive VP – Burlington, MA), Gould Electronics Imaging & Graphics (President & General Manager – San Jose, CA), ATP (Chairman and CEO – Campbell, CA), and Mentor Graphics Corporation (VP & General Manager – PCB Division San Jose, CA & Professional Services Division – Wilsonville, OR).
Henke is a Fellow of the Society of Manufacturing Engineers (SME) and served on the SME International Board of Directors. Henke was also a board member of SDRC, PDA, ATP, and the MacNeal Schwendler Corporation, and he currently serves on the board of Stottler Henke Associates, Inc. (San Mateo, CA). He also serves as VP Business Development of Stottler Henke, focused on commercial applications of artificial intelligence.
In addition, Henke is a member of the IEEE and a Life Fellow of ASME International. In April 2006, Dr. Henke received the 2006 Lifetime Achievement Award from the CAD Society, presented by CAD Society president Jeff Rowe at COFES2006 in Scottsdale, AZ. In February 2007, Henke became affiliated with Cyon Research’s select group of experts on business and technology issues as a Senior Analyst. This Cyon Research connection aids and supplements Henke’s ongoing, independent consulting practice (HENKE ASSOCIATES).
Dr. Henke has also been a contributing editor of the EDACafé.com EDA WEEKLY, and he has published EDA WEEKLY articles every four weeks since November 2009; all URL’s available at:
Since May 2003 HENKE ASSOCIATES has also published more than 100 independent COMMENTARY articles on MCAD, PLM, EDA and Electronics IP on IBSystems’ MCADCafé.com and EDACafé.com; most URL’s available. Click on Editorials on the toolbar on the front page of EDACafe.com. and then click on EDA Commentary.
Complete information on HENKE ASSOCIATES is available at: http://www.henkeassociates.net.
March 31, 2012 marks the 16th Anniversary of the founding of HENKE ASSOCIATES.
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