Archive for the ‘Uncategorized’ Category
Monday, October 24th, 2016
October continues to be a busy month. I’m just back from a whirlwind trip to Munich, Germany, for DVCon Europe where I was the keynote speaker at the Wednesday night dinner. Stay tuned for a full report in my next blog post.
Meanwhile, if you’re going to ARM TechCon this week, please stop by the ESD Alliance Booth (#523) where you can learn about our programs and new initiatives and pick up a copy of our quarterly newsletter. The Expo Hall will be open Wednesday and Thursday from 10:30 a.m. until 6:30 p.m. at the Santa Clara Convention Center, Santa Clara, Calif.
Thursday, October 13th, 2016
The ESD Alliance’s Emerging Companies Committee has a great topic, excellent moderator and an impressive group of panelists for the second in our ongoing series of panels on legal issues affecting small and emerging technology companies.
“Legal Steps to Maximize your Exit Value” will be held Tuesday, November 1, from 6 p.m. until 9 p.m. at Cadence’s corporate headquarters in San Jose, Calif. Attendees will learn about key valuation issues and techniques, along with more nuanced positioning strategies to build and lock-in enterprise value on exit transactions.
Wednesday, October 5th, 2016
Many thanks to Peggy Aycinena whose blog post is found above mine for her great profile of this year’s Phil Kaufman Award recipient, Andrzej Strojwas (pronounced Andrey Stroyvas), Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. If you haven’t read it as yet, I highly recommend it.
Andrzej is being recognized with the award, presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA), for his pioneering research in the area of design for manufacturing (DFM) in the semiconductor industry. The relationship between design and manufacturing has never been more important and Andrzej deserves praise for recognizing early on that DFM needed to be a key element of chip design automation. His work was instrumental in bringing design and manufacturing together in a way that has benefited the semiconductor design and manufacturing communities as well as the broader electronics products markets.
The Phil Kaufman Award Ceremony and Dinner to honor him will be held January 26 at the Fourth Street Summit Center in San Jose, Calif., where we held last year’s dinner paying tribute to Mentor Graphics’ Wally Rhines. Wally was honored for growing the EDA and IC design industries through his efforts as a leading voice of EDA and for pioneering the evolution of IC design to SoC design.
Monday, September 5th, 2016
While many things keep me awake at night, concerns about IP tracking and security must keep many chip project managers from getting a restful sleep. That’s what convinced Warren Savage, chair of the ESD Alliance’s Semiconductor IP Working Group and general manager of Silvaco’s IP Division, to organize a panel “Semiconductor IP Issues that Keep You Up at Night.” It will be held Wednesday, September 14, from 6 p.m. until 8:30 p.m. at Silvaco’s offices in Santa Clara, Calif. Light snacks and beverages will be served during the networking hour from 6 p.m. until 7 p.m.
Warren will start the evening with an overview of the IP landscape. A panel will follow with experts Eric Stein from PwC and Rob Ballow of KPMG, who will share their advice on best practices, offer ways to implement them and answer audience questions. Eric and Rob are leading authorities on IP compliance from two of the largest worldwide auditing firms.
According to Warren, the massive amount of IP reuse involved in building an SoC has created a “big data” problem that is poorly managed by industry standards or methodologies. Instead, IP companies face a situation where their IP may be used without the proper license, leading to millions of dollars of lost revenue. Semiconductor companies face different issues but equally troubling as their engineers may inadvertently expose them to potentially huge liabilities as a result of “accidentally” reusing a core without the proper license. Warren, Eric and Rob will outline commonly used practices used today and discuss new technologies that may help both buyers and sellers rest easier.
This event is open to all ESD Alliance member companies free of charge. Non-ESD Alliance members are welcome to attend at a cost of $40, payable online or at the door. For more information, click here. To register, click register.
As an expert in IP design and reuse, Warren worked with the Alliance to form the Semiconductor IP Working Group, our newest initiative. The group is working on a common methodologies and best practices for fingerprinting, and an end-to-end solution for tracking and auditing soft and hard IP that benefits both IP developers and vendors as well as IP users.
As I mentioned in several earlier blog posts, please contact me if your company is considering joining the ESD Alliance. Member companies will be eligible to receive information from or participate in the SIP Working Group’s efforts. Additionally, employees of member companies can participate in the SIP Working Group or some of the other initiatives offered by the Alliance. I’m always available to answer any questions about the Alliance and why your company should join. Please contact me at firstname.lastname@example.org.
Join us September 14 and have a better night’s sleep! We look forward to seeing you. For more information about the ESD Alliance, visit: www.esd-alliance.org.
Monday, August 1st, 2016
Anyone in our industry who doesn’t believe system scaling is an industry movement need look no further than the IoT market of high-volume and low-cost devices. While these devices have exacting densities, performance and power requirements, advanced process technologies are a bit too risky and costly for IoT developers. IoT also requires heterogeneous functions such as digital, analog, mixed-signal, sensors and MEMS, a challenging proposition to mix all of these capabilities on a single die/process.
And, system scaling –– or multi-die IC –– is a viable integration alternative to traditional transistor scaling of newer process technologies. It integrates complex systems at the functional/building block level, not the transistor level. It doesn’t replace the need for the SoC. Instead, the SoC remains a key functional component of the system or, in die-form, a key building block of a multi-die IC. System scaling relies on different advanced packaging technologies used to integrate and package multiple heterogeneous die.
Monday, July 11th, 2016
If you are planning to attend SEMICON West, please put the ESD Alliance booth on your Must See list so you can learn more about us. We will be in booth N1 in the North Hall at the Moscone Center in San Francisco. Exhibit hours are Tuesday, July 12, and Wednesday, July 13, from 10 a.m. until 5 p.m., and Thursday, July 14, from 10 a.m. until 4 p.m.
During SEMICON West, I will be a panelist on “The Path to Semiconductor and MEMS/Sensors Common Best Practices for Growth” discussion Wednesday from 2 p.m. until 3 p.m. It’s part of a workshop organized by SEMI and the MEMS & Sensors Industry Group titled, “From Collision to Convergence: Co-Creating Solutions in the Semiconductor and MEMS/Sensors Industries.” The workshop will run from 1 p.m. until 5 p.m. at the Marriott Marquis, just blocks from the Moscone Center.
To learn more, visit: http://www.semiconwest.org/
In case you missed it, here’s the link to the quarterly Market Statistics Service (MSS) report we published last week. It contains detailed revenue data for the EDA, Semiconductor IP, and design services industries. Overall, in first quarter 2016, we’re pleased to report industry revenues increased 4.5% compared to Q1, 2015. Total revenue for Q1 was $1962 million.
Wednesday, June 15th, 2016
The Design Automation Conference is over. The cowboy boots, 10-gallon hats and “Keep Austin Nerdy” T-shirts have been put in storage until DAC returns to Austin next year. For those of you from the electronic system design ecosystem who didn’t get to Austin this year, here’s a look at what you missed.
The parties –– from the opening reception, Jim Hogan’s Heart of Technology and IPextreme’s annual Stars of IP party hosted by Silvaco to the not-to-be missed Cadence’s Denali evening –– were lively, the Pavilion panel sessions and keynotes well attended and the giveaways were first rate.
Exhibitor feedback was positive, from my sampling, though you may have heard that attendance was down in Austin. While the attendee numbers haven’t been posted as yet, exhibitors didn’t seem phased by the perceived lower attendance. In fact, many noted that while the traffic at the show was smaller than in San Francisco, it provided higher quality attendees and more highly qualified prospects.
DAC was a great opportunity for the new Electronic System Design (ESD) Alliance to “strut our stuff” (minus the cowboy boots and Stetsons). Attendees and exhibits showed loads of interest in the new organization and stopped by our booth to learn more about our new, expanded direction and initiatives. Better yet, several companies committed to joining the Alliance based on our refreshed mission and momentum. Many others have asked us to follow up over the coming months.
Thursday, June 2nd, 2016
A reminder that the ESD Alliance –– a proud DAC co-sponsor –– will exhibit at DAC in Booth (#1920) Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center, Austin, Texas. Please stop by our booth to say hello and to learn more about our support of the Design Ecosystem. We’ll have plenty of informational handouts, including the latest edition of our newsletter, brochures on our new initiatives and membership packets.
Or, join us at the DAC Pavilion (Booth #1839) for, “Solving the Design Cost Puzzle: How intellectual property (IP) Fits,” featuring Jim Feldhan, president of Semico Research, Tuesday from 10:30 a.m. until 11 a.m. Jim will address trends and issues driving the rapidly growing market for third-party IP.
You’ll find many of us from the Alliance at the Gary Smith EDA kickoff Sunday from 5 p.m. until 5:30 p.m. in the convention center’s Ballroom D. Laurie Balch, a chief analyst for Gary Smith EDA, will open the annual reception with the annual update on the state of EDA, “Extending the Bounds of EDA.” The always well-attended DAC reception immediately follows.
Thursday, May 19th, 2016
The Design Automation Conference (DAC) is only a few short weeks away and the Electronic System Design Alliance will be there in full force. We continue to be a proud DAC co-sponsor –– a distinction we’ve had since 1992 –– and we’ll have a booth on the exhibit floor again this year. I hope you’ll stop by our booth (#1920) to learn more about the Alliance, our expanded mission and new initiatives in support of the Design Ecosystem. Exhibits will be open Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas.
We will host a DAC Pavilion (Booth #1839) talk, “Solving the Design Cost Puzzle: How intellectual property (IP) Fits,” featuring Jim Feldhan, president of Semico Research, Tuesday from 10:30 a.m. until 11 a.m. He will address trends and issues driving the rapidly growing market for third-party IP. This follows our joint announcement in April about a cooperative marketing partnership between Semico and the ESD Alliance to work together on several business initiatives in support of the semiconductor design ecosystem.
Wednesday, April 27th, 2016
We’re in the process of forming a working group on system scaling and welcome your input as a member of the chip design or semiconductor manufacturing ecosystems to help us set the direction. Join us for an open forum, “More than Moore –– Enabling the Power of System Scaling,” Tuesday, May 17, from 6 p.m. until 8:00 p.m. at the ESD Alliance/SEMI Global Headquarters in San Jose, Calif.
The host for the evening will be Herb Reiter of eda 2 asic Consulting who will lead a discussion on what it will take to propel system scaling solutions into the mainstream for semiconductor design and manufacturing. The goal of the meeting is to help the ESD Alliance identify priorities in both the manufacturing and design areas that will help unlock the potential of system scaling.
System scaling offers an alternative path to pursuing Moore’s Law by moving the integration focus from the transistor to the integration of heterogeneous pre-fabricated and proven devices, including die-level IP, into an advanced IC package. As Herb points out, there are various system scaling technologies already in use today, such as interposer-based designs using die-level IP blocks, but they have not crossed into the mainstream. Although new sub-10nm process technologies continue to drive Moore’s Law, development costs at these advanced nodes are beyond the reach of much of the conventional market.
Here’s where the ESD Alliance comes in. As an industry organization, we can facilitate interaction between modeling, design, analysis/verification, manufacturing and test in order to unlock the potential of these new integration solutions. We see the formation of the System-Scaling Working Group as a way to bring manufacturing and automation together to enable efficient and cost-effective use of advanced packaging technologies. The Alliance will be able to focus on expanding automation coverage and modeling, helping the industry leverage Moore’s Law in a new and powerful way. Most important, we see opportunities for our members to grow their businesses in automation, modeling and manufacturing.