Archive for the ‘Uncategorized’ Category
Thursday, June 2nd, 2016
A reminder that the ESD Alliance –– a proud DAC co-sponsor –– will exhibit at DAC in Booth (#1920) Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center, Austin, Texas. Please stop by our booth to say hello and to learn more about our support of the Design Ecosystem. We’ll have plenty of informational handouts, including the latest edition of our newsletter, brochures on our new initiatives and membership packets.
Or, join us at the DAC Pavilion (Booth #1839) for, “Solving the Design Cost Puzzle: How intellectual property (IP) Fits,” featuring Jim Feldhan, president of Semico Research, Tuesday from 10:30 a.m. until 11 a.m. Jim will address trends and issues driving the rapidly growing market for third-party IP.
You’ll find many of us from the Alliance at the Gary Smith EDA kickoff Sunday from 5 p.m. until 5:30 p.m. in the convention center’s Ballroom D. Laurie Balch, a chief analyst for Gary Smith EDA, will open the annual reception with the annual update on the state of EDA, “Extending the Bounds of EDA.” The always well-attended DAC reception immediately follows.
Thursday, May 19th, 2016
The Design Automation Conference (DAC) is only a few short weeks away and the Electronic System Design Alliance will be there in full force. We continue to be a proud DAC co-sponsor –– a distinction we’ve had since 1992 –– and we’ll have a booth on the exhibit floor again this year. I hope you’ll stop by our booth (#1920) to learn more about the Alliance, our expanded mission and new initiatives in support of the Design Ecosystem. Exhibits will be open Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas.
We will host a DAC Pavilion (Booth #1839) talk, “Solving the Design Cost Puzzle: How intellectual property (IP) Fits,” featuring Jim Feldhan, president of Semico Research, Tuesday from 10:30 a.m. until 11 a.m. He will address trends and issues driving the rapidly growing market for third-party IP. This follows our joint announcement in April about a cooperative marketing partnership between Semico and the ESD Alliance to work together on several business initiatives in support of the semiconductor design ecosystem.
Wednesday, April 27th, 2016
We’re in the process of forming a working group on system scaling and welcome your input as a member of the chip design or semiconductor manufacturing ecosystems to help us set the direction. Join us for an open forum, “More than Moore –– Enabling the Power of System Scaling,” Tuesday, May 17, from 6 p.m. until 8:00 p.m. at the ESD Alliance/SEMI Global Headquarters in San Jose, Calif.
The host for the evening will be Herb Reiter of eda 2 asic Consulting who will lead a discussion on what it will take to propel system scaling solutions into the mainstream for semiconductor design and manufacturing. The goal of the meeting is to help the ESD Alliance identify priorities in both the manufacturing and design areas that will help unlock the potential of system scaling.
System scaling offers an alternative path to pursuing Moore’s Law by moving the integration focus from the transistor to the integration of heterogeneous pre-fabricated and proven devices, including die-level IP, into an advanced IC package. As Herb points out, there are various system scaling technologies already in use today, such as interposer-based designs using die-level IP blocks, but they have not crossed into the mainstream. Although new sub-10nm process technologies continue to drive Moore’s Law, development costs at these advanced nodes are beyond the reach of much of the conventional market.
Here’s where the ESD Alliance comes in. As an industry organization, we can facilitate interaction between modeling, design, analysis/verification, manufacturing and test in order to unlock the potential of these new integration solutions. We see the formation of the System-Scaling Working Group as a way to bring manufacturing and automation together to enable efficient and cost-effective use of advanced packaging technologies. The Alliance will be able to focus on expanding automation coverage and modeling, helping the industry leverage Moore’s Law in a new and powerful way. Most important, we see opportunities for our members to grow their businesses in automation, modeling and manufacturing.
Tuesday, April 19th, 2016
It’s been only a few short weeks since we launched the Electronic System Design (ESD) Alliance and we haven’t stopped there.
The party March 30 was a huge success, with more than 100 members of the design ecosystem community helping us celebrate our new name and expanded mission. The pictures show the support and enthusiasm better than I can in words. The slideshow can be found at: http://bit.ly/1SQnfF6
For a look at why we made the sweeping changes, check out the March 31 news release found at: http://bit.ly/1Sg4NrV
Next up, we announced last week that well-known visionary, leader and technology investor Lucio Lanza, managing director of Lanza techVentures, has been appointed to the Board of Directors. We are especially pleased that he accepted the board’s invitation because he has tremendous insights and an astute understanding of the market. Fittingly, Lucio was the recipient of the Phil Kaufman Award for Distinguished Contributions to EDA in 2014 for his substantial impact on EDA through his strategic and financial assistance to innovative EDA companies. Welcome, Lucio! The news release with details can be found at: http://bit.ly/1YyfU0Z
Thursday, March 24th, 2016
We’re only a few short days away from unveiling the EDA Consortium’s new name, new look and expanded mission to move us into the future. Based on the RSVPs, we’re expecting a huge crowd at our launch party Wednesday, March 30, that will feature wine and craft beer tasting and hors d’oeuvres. Don’t miss out on this stellar networking opportunity –– we have some of the industry’s top leaders coming.
Yes, the evening is meant to be a social gathering to celebrate the future of the Semiconductor design ecosystem, the critical driver of the worldwide semiconductor and electronic products markets. We’ll toast our storied past as well. I’ll interrupt the festivities with a short presentation on the new EDAC and will take the wraps off our new name and new look.
It’s not too late to register to join us. Everyone is welcome. The evening, open free of charge, starts at 6:30 p.m. and will run until 8:30 p.m. at the EDA Consortium/SEMI Global Headquarters, 3081 Zanker Road in San Jose, Calif. For registration details, go to: http://goo.gl/VBrezS
We look forward to seeing you and sharing our vision.
Wednesday, March 9th, 2016
The EDA Consortium is moving into the future and you’re invited to help us celebrate at a launch party where we will unveil our new name, expanded mission and a new look.
Our wine and craft beer tasting evening with hors d’oeuvres will be held Wednesday, March 30, starting at 6:30 p.m. and running until 8:30 p.m. We’ll be at the EDA Consortium/SEMI Global Headquarters, 3081 Zanker Road in San Jose, Calif.
Many longtimers will remember when EDAC was formed in 1989 to address cross-industry issues and promote the EDA industry. It was the “go-go” years for electronic design automation that seemed never-ending and our tagline said it all: “Where Electronics Begins.” Lively EDAC events became the place to network. We became a co-sponsor of DAC in 1992. In 1994, the Market Statistics Service (MSS) reporting began. The Phil Kaufman Award was created that year as well and presented to Hermann Gummel, a Semiconductor and EDA industry pioneer.
Monday, February 22nd, 2016
I’m out of town this week with the DAC Executive Committee –– EDAC is one of DAC’s three sponsors ––as we put the finishing touches on this
year’s program. While details won’t be available for a few more weeks, I can say that the program is looking very strong this year with a lot of technical diversity including security, IoT, automotive, IP, and a few more surprises.
Tuesday, February 16th, 2016
We’re an industry filled with exceptional individuals, 21 of whom have been singled out and heralded by being recipients of the Phil Kaufman Award for Distinguished Contributions to Electronic Design Automation (EDA) Award since it was established in 1994.
It’s time once again to consider a deserving individual for this prestigious award presented yearly by the EDA Consortium (EDAC) and the IEEE Council on EDA (CEDA). Nominations are open and will be accepted until Thursday, June 30.
As you know, Dr. Walden (Wally) C. Rhines, chairman and chief executive officer of Mentor Graphics Corporation, was the recipient of the 2015 award. He was honored for growing the EDA and IC design industries through his efforts as a leading voice of EDA and for pioneering the evolution of IC design to SoC design.
Wednesday, February 3rd, 2016
Now, there’s another reason to head to the DoubleTree Hotel in San Jose, Calif., the week of February 29. Yes, the annual DVCon kicks off Monday, February 29, with a day full of tutorials and the DVCon Expo and Booth Crawl that begins at 5 p.m.
Tuesday evening, March 1, EDAC and our Emerging Companies Committee will host the next “Crossing the Chasm: From Technology to Valuable Enterprise.” Jim Hogan will chat with Dr. Ajoy Bose, former chairman, president and CEO of Atrenta, about how Atrenta successfully crossed the chasm, moving from technology company to valuable enterprise acquired by Synopsys.
The evening will start at 6 p.m., just as the DVCon exhibits close for the day. A networking session with light refreshments will be held from 6-7 p.m. The discussion will begin at 7 p.m. DVCon attendees are welcome to join us.
Everyone reading this blog knows or has heard of Jim Hogan, an indefatigable promoter of EDA, and the series he created on the entrepreneurial experience. An earlier blog features an interview with Jim on this popular event.
Wednesday, January 20th, 2016
Let’s tip our glass of champagne to 2016, which started off on a high note for the EDA industry. The EDA Consortium’s Market Statistics Service (MSS) reported revenue for Q3 2015 increased 7.1 percent to $1957.5 million compared to $1828.1 million in Q3 2014.
Coverage of our news was positive on our industry onlines and elsewhere, though there was an interesting “first” in the numbers that deserves highlighting. In Q3 2015, the Semiconductor IP (SIP) segment showed the highest revenue out of all categories tracked by the MSS at $653 million. For the first time, SIP exceeded Computer Aided Engineering (CAE) at $635 million.
What a difference 20 years makes! Back in Q3 1996, SIP was the smallest revenue category being tracked and showed $15 million in revenue. Taken over the past 20 years, the SIP segment has grown, on average, at 20% per year –– a seemingly remarkable achievement. Or is it?
The IP revolution has been underway for quite some time and has had a profound impact on electronics design. Chips now are a collection of small and large blocks of IP stitched together along with value-added circuitry created by the chip design team. It is not uncommon to find that IP blocks make up 60-70% or even more of the real estate on these large chip designs.