Archive for the ‘Uncategorized’ Category
Thursday, July 6th, 2017
It’s been a busy few weeks since DAC and full of good news from the ESD Alliance. First, we welcomed our newest member EDDR Software, developer of custom and open source enterprise solutions for semiconductor design. According to Kevin Nesmith, EDDR Software’s CEO, “The ESD Alliance has the potential to open opportunities for us to partner with other member companies to create better solutions for users. We look forward to participating in working groups to help set the direction of the semiconductor design ecosystem.” The news release with more information is available at: http://bit.ly/2uvpTfo
More good news as our latest Market Statistics Service (MSS) report shows the EDA industry revenue increased 10.5 percent for Q1 2017 to $2167.5 million, compared to $1962 million in Q1 2016. “The EDA industry reported double-digit growth in Q1, led by gains in the two largest categories, CAE and Semiconductor IP,” reports Wally Rhines, board sponsor for the MSS and president and CEO of Mentor, a Siemens business. “The two largest regions, Americas and Asia-Pacific, also reported double-digit growth in Q1.” For more details, see the news release at: http://bit.ly/2suTCUk
Thursday, June 22nd, 2017
Congratulations to SoC Solutions and Silvaco! SoC Solutions will soon be under the Silvaco umbrella. (See the news release, “Silvaco to Acquire SoC Solutions.”
As a member of the ESD Alliance, SoC Solutions recently took full advantage of the well-honed expertise of our Export Committee. In fact, as SoC Solutions found, anyone who doubts the value of the ESD Alliance or its Export Committee won’t after learning that the three-person group took on the U.S. Department of Commerce’s Bureau of Industry and Security (BIS) and won.
Yes, consider the Export Committee formidable. Made up of representatives from Synopsys, Mentor and Cadence, it was able to persuade BIS to change a small but important piece of the Encryption and Export Administration Regulations. “In our EDA world, we have one main exemption that my committee gained for the industry back in 2005 –– decontrolling our usage of encryption in the design cycle,” says Cadence’s Larry Disenhof, the chair of the Export Committee. Only in the last year has the main body of encryption regulations caught up with our exemption fully decontrolling ancillary encryption used in products from DVD players and household appliances to protection of IP in electronic design, he added. “Without this exemption, we would have been filing license applications constantly for the last 10 years.”
Thursday, June 8th, 2017
The following week, we’re off with rest of the semiconductor design ecosystem to Austin, Texas, for the Design Automation Conference (DAC). Events kick-off Sunday, June 18, and go through Thursday, June 22, with exhibits running Monday through Wednesday from10 a.m. until 6 p.m. at the Austin Convention Center.
The opening event, “Electronic Design Automation (EDA) in the Age of the System,” will update attendees on the state of EDA. Chief Analyst Laurie Balch of Gary Smith EDA will present the firm’s findings at this ESD Alliance-hosted event Sunday from 5 p.m. until 5:30 p.m. in Ballroom D of the convention center. A DAC reception immediately follows on the Fourth Floor Foyer.
We’re pleased that so many of our board members will have visible roles in the DAC program, starting with Amit Gupta, president and CEO from Solido, who will moderate a panel titled, “EDA Powered by Machine Learning,” It will be held Monday in Room 10AB from 10:30 a.m. until 11:30 a.m
A “One-On-One” discussion with Lip-Bu Tan, president and CEO of Cadence, and Ed Sperling, editor-in-chief of Semiconductor Engineering, will be held Monday from 11:30 a.m. until 12:15 p.m. at the DAC Pavilion. Lip-Bu will share insights about big changes in the data center and end markets, the rise of machine learning, growing challenges in system design, and what to watch for in China.
Thursday, May 25th, 2017
The ESD Alliance has a new look with a refreshed website, thanks to our tenacious Member of the Technical Staff Paul Cohen who oversaw the entire project.
And, what a project it was! The design streamlines our activities, all found in neatly packaged pull-down sections running across the top right of the home page. You’ll find information about us, including the staff, board of directors, committees and member companies. Our active initiatives provide the forum for member companies to address issues of common concern and fall broadly into five categories –– risk management, growth and efficiency, industry voice, events and education, and market information. All are outlined in detail and we invite participation from member companies. Naturally, we have a section on news and events that hosts our newsletters and my blog. More content is being added regularly. Please let Paul (email@example.com) or me (firstname.lastname@example.org) know what you think.
Of course, the next event is the Design Automation Conference (DAC), the premier conference for design and automation of electronic systems, long sponsored by the ESD Alliance. DAC is being held this year at the Austin Convention Center in Austin, Texas.We’ll be in booth #2123 Monday-Wednesday, June 19-21, from 10 a.m. until 6 p.m.
Please stop by our booth to see us. We’ll have our latest newsletter and other handouts. And, make sure you visit our member companies’ DAC booths as well. By all means, tell them I sent you!
Tuesday, May 9th, 2017
One of the most popular and enduring programs the ESD Alliance offers its members is the quarterly Market Statistics Service (MSS) report containing detailed revenue data for the EDA, Semiconductor IP and design services industries. The report compiles data submitted confidentially by public and private EDA and semiconductor IP companies into tables and charts listing the data by product category and geographic region.
The chart above shows the MSS Revenue by category from 1996 through 2016.
Tuesday, April 25th, 2017
Please join me in welcoming two new members of the ESD Alliance –– CAST and SoC Solutions –– both of whom are semiconductor IP providers and intend to become active members of our SIP Working Group.
CAST of Woodcliff Lake, N.J., has 23 years of SIP experience and offers a range of production-proven SIP cores that include controllers and processors, compression, peripherals, interconnect and security, and encryption.
SoC Solutions from Suwanee, Ga., enables next-generation IoT and Machine to Machine (M2M) silicon devices by supplying processor-based IP and services to build innovative, low-power “connected” products.
According to Jim Bruister, SoC Solutions’ CEO: “The ESD Alliance is the all-important connection to the semiconductor design ecosystem. For a company like ours, there’s no better organization to belong to for both the networking opportunities and the Semiconductor IP Working Group that’s helping to define so many critical aspects of our market segment.”
Thursday, April 20th, 2017
The semiconductor design ecosystem came out in force Thursday, April 6, for the CEO Outlook at Synopsys in Mountain View, Calif. It was a great crowd and an exceptional panel moderated by Semiconductor Engineering’s Ed Sperling. Thanks to Lip-Bu Tan of Cadence, Wally Rhines from Mentor, ARM’s Simon Segars and Aart de Geus at Synopsys for their insights and a lively discussion.
Our special guests that night were from the Dwight D. Eisenhower School for National Security and Resource Strategy, part of the National Defense University (NDU). The ESD Alliance hosts a yearly visit from the NDU students and organizes meetings with noted semiconductor companies in Silicon Valley to help educate them about our industry and its importance to the global electronics industry.
A picture is worth a thousand words, so I’ll dispense with a long blog and let the photos tell the story.
If you’re craving words to describe the evening, Peggy Aycinena wrote a blog filled with color and loads of details on EDACafe. It can be found at: http://bit.ly/2kjVajD
From left to right: ESD Alliance Board Chair Grant Pierce of Sonics, the ESD Alliance’s Julie Rogers, Wally Rhines, Aart de Geus, Paul Cohen of the ESD Alliance and Larry Disenhof of Cadence.
Ed Sperling of Semiconductor Engineering (at left) with panel members and ESD Alliance Board Member (from left to right) Lip-Bu Tan of Cadence, Wally Rhines from Mentor Graphics, ARM’s Simon Segars and Aart de Geus of Synopsys.
Tuesday, March 28th, 2017
The spectacular news this week from the ESD Alliance’s Market Statistics Service (MSS) that revenue increased 18.9 percent for Q4 2016 will be an exclamation point to next week’s CEO Outlook.
For example, revenue for Q4 in all four geographic regions –– Americas, Europe, Middle East and Africa, and Japan and Asia/Pacific –– increased 18.9 percent for Q4 2016 to $2455 million, compared to $2064.5 million in Q4 2015. All product categories saw fourth-quarter growth. In fact, CAE, Semiconductor IP, IC Physical Design & Verification and PCB/MCM reported double-digit increases. Another positive sign is employment is up 6.6% overall.
CEO Outlook attendees can expect to hear much more about industry opportunities for growth and challenges as Ed Sperling, editor-in-chief of Semiconductor Engineering, moderates the panel of four of our most visible CEOs and Alliance Board Members. They are: Aart de Geus, CEO at Synopsys, Lip-Bu Tan, president and CEO of Cadence, ARM’s CEO Simon Segars and Wally Rhines, chairman and CEO of Mentor Graphics and board sponsor for the MSS.
Friday, March 17th, 2017
Please Note: With regrets, we are postponing the “Energy Policy and Strategy for the IoT Era,” the panel on the new energy rules for PCs from the California Energy Commission Thursday, March 23, due to unforeseen circumstances. Stay tuned for updates.
After listening to our members who told us they missed the yearly CEO forecast, it’s a pleasure to let you know the ESD Alliance is bringing back an evening with the leaders of our industry. The 2017 CEO Outlook will be held Thursday, April 6, from 6:30pm until 8:45pm at Synopsys in Mountain View, Calif. A private reception for ESD Alliance members only to mingle with speakers will begin at 5:30pm.
Four of our industry’s most visible CEOs will discuss their views on the future of the system design ecosystem in what promises to be a wide-ranging and enlightening panel discussion. The four panelists for the evening are: Aart de Geus from Synopsys, Lip-Bu Tan of Cadence, ARM’s Simon Segars and Wally Rhines of Mentor Graphics. Each will share his views on where the semiconductor industry and system design ecosystem are heading, review trends and point out potential opportunities and danger signs ahead. After brief opening statements about the future of the industry, an interactive audience discussion will follow.
Tuesday, March 7th, 2017
Fresh from our “Ride with the Verify Seven” evening co-hosted with ESD Alliance member company OneSpin during DVCon, we’re planning our next event with another member company –– Sonics –– Thursday, March 23.
The panel, “Energy Policy and Strategy for the IoT Era,” moderated by Grant Pierce, Sonics’ CEO and chairman of the Alliance board of directors, will outline new energy rules for PCs set by the California Energy Commission (CEC). A panel discussion will look at how these new rules affect the system design ecosystem and how the industry will adapt to them.
The standards, primed to begin January 1, 2018 and roll out through July 2021, cover desktop computers, notebooks and laptops, small-scale servers, workstations and monitors, the top consumers of electricity in California. Estimates are staggering –– the state reports consumption of about 5,610 gigawatt hours of electricity or 3% of residential electricity use and 7% commercial. The CEC determined something needed to change, even though many manufacturers build seemingly energy-efficient products. The new standards are estimated to save 2,332 gigawatt hours per year and reduce utility bills by more than $370 million, enough energy to power about 350,000 California homes a year while reducing greenhouse gas emissions.