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March 23: An Evening on Energy Efficiency from the ESD Alliance and Sonics

Tuesday, March 7th, 2017

Fresh from our “Ride with the Verify Seven” evening co-hosted with ESD Alliance member company OneSpin during DVCon, we’re planning our next event with another member company –– Sonics –– Thursday, March 23.

The panel, “Energy Policy and Strategy for the IoT Era,” moderated by Grant Pierce, Sonics’ CEO and chairman of the Alliance board of directors, will outline new energy rules for PCs set by the California Energy Commission (CEC). A panel discussion will look at how these new rules affect the system design ecosystem and how the industry will adapt to them. 

The standards, primed to begin January 1, 2018 and roll out through July 2021, cover desktop computers, notebooks and laptops, small-scale servers, workstations and monitors, the top consumers of electricity in California. Estimates are staggering –– the state reports consumption of about 5,610 gigawatt hours of electricity or 3% of residential electricity use and 7% commercial. The CEC determined something needed to change, even though many manufacturers build seemingly energy-efficient products. The new standards are estimated to save 2,332 gigawatt hours per year and reduce utility bills by more than $370 million, enough energy to power about 350,000 California homes a year while reducing greenhouse gas emissions.
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Photos from the Phil Kaufman Award Ceremony and Dinner, A Night to Remember

Friday, February 24th, 2017

The Super Bowl wasn’t the only festive event over the last few weeks! The Electronic Systems Design ecosystem honored Andrzej Strojwas as the 2016 Phil Kaufman Award recipient during an awards ceremony and dinner attended by close to 200 of us from the industry. It was held Thursday, January 26, at the Fourth Street Summit Center in San Jose, Calif.

Caption: Kaufman Award recipient Andrzej Strojwas (standing in the middle with his statuette), along with his extended family, PDF Solutions and Carnegie Mellon colleagues and graduate students.

For those of you who don’t know Dr. Strojwas, he is PDF Solutions’ chief technologist as well as the Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. He was recognized with the award for his pioneering research in the area of DFM in the semiconductor industry.

The Kaufman Award is presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA). For more information, check out: http://bit.ly/2l95wTO

As I did with the RISC-V event, I won’t try to recapture the evening when two of our favorite chroniclers Peggy Aycinena and Paul McLellan covered the evening so masterfully and neatly depicted the mood. (See the links to their blog posts below.) Instead, I’ll offer you a look at who was there through photos taken by the Alliance’s Paul Cohen and Julie Rogers and ace photographer Ross Mehan of Ross Mehan Photography. The video, produced by Andrew Mellows Video, will be available on the ESD Alliance website shortly.

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ESD Alliance Bulletin: DVCon, New Member Helic, Upcoming Events

Thursday, February 23rd, 2017

I promised in my last post a special blog post with great photos highlighting the Phil Kaufman Award Ceremony and Dinner January 26. It will go up Monday.

But first, the news that the ESD Alliance will exhibit at DVCon at the DoubleTree Hotel in San Jose, Calif. We’ll be in Booth #100 in the foyer, so please stop by if you’re attending.

During DVCon, we’re co-hosting with OneSpin Solutions a panel, “Ride with the Verify Seven,” moderated by Jim Hogan of Vista Ventures featuring six verification leaders who grew their companies from startup to medium-sized industry player. It will be held Monday beginning at 7 p.m., after the Booth Crawl, until 8:30 p.m. Light refreshments and drinks will be served.

Panelists include:

  • Andy Stein, Vice President of North American Sales from Avery Design Systems
  • Adnan Hamid, CEO at Breker Verification Systems
  • Phil Moorby, Chief Architect of Montana, a Phil Kaufman Award recipient presented to him by the ESD Alliance and IEEE CEDA for inventing the Verilog language
  • Raik Brinkmann, President and CEO of OneSpin, an ESD Alliance Member Company
  • Prakash Narain, President and CEO at Real Intent, an ESD Alliance Member Company
  • Rick Carlson, ESD Alliance Member Company Verific’s Vice President of Sales and advisor to seven early-stage startups

The event is open free of charge to all Alliance member companies and DVCon attendees. Non-members of the Alliance or anyone without a DVCon badge are invited to attend for a fee of $40. Registration information and more details on the event can be found at: http://bit.ly/2kNWx6T

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Come Ride with the Verify Seven, the Next-Gen Verification Leaders

Friday, February 17th, 2017

I’m now able to share with EDACafe readers the news about an exciting evening panel we’re co-hosting with OneSpinSolutions titled, “Ride with the Verify Seven,” during DVCon Monday, February 27.

It will be moderated by industry luminary Jim Hogan of Vista Ventures and features six well-known and readily recognizable verification leaders who grew their companies from startup to medium-sized industry player:

  • Andy Stein, Vice President of North American Sales from Avery Design Systems
  • Adnan Hamid, Chief Executive Officer (CEO) at Breker Verification Systems
  • Phil Moorby, Chief Architect of Montana, a Phil Kaufman Award recipient presented to him by the ESD Alliance and IEEE CEDA for inventing the Verilog language
  • Raik Brinkmann, President CEO of OneSpin
  • Prakash Narain, Real Intent’s President and CEO
  • Rick Carlson, Verific’s Vice President of Sales and advisor to seven early-stage startups

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Save the Date! The ESD Alliance/OneSpin Solutions Sponsor DVCon Event

Monday, February 13th, 2017

Please save Monday evening, February 27, during DVCon for an entertaining but informative and inspiring panel discussion with today’s emerging verification leaders. Sponsored by the ESD Alliance and OneSpin Solutions, the discussion will be moderated by the always enthusiastic Jim Hogan who will tease out how they are succeeding in a market where much larger competitors also participate.

We plan to start right after the DVCon Expo Booth Crawl that runs from 5-7pm. We’ll have drinks and snacks and there will be planey of opportunity to network. DVCon will be held at the Doubletree Hotel, San Jose, Calif.

Watch this space for more details on who’s participating in the discussion and the room where it will be held.

Grant Pierce to Chair ESD Alliance Board of Directors

Thursday, February 9th, 2017

I’m pleased to be able to announce that Grant Pierce, CEO of Sonics, Inc., was elected by the ESD Alliance Board of Directors to serve as chairman. Grant and I have had the opportunity to work together on several Alliance projects and I welcome the chance to work more closely with him. He is an active board member, whose varied industry experience and well-honed skillset will help us forge ahead.

Grant Pierce

Grant is quoted in our news release as saying: “It is an honor and a privilege to be named chairman of the ESD Alliance by my peers on the board. This is a great opportunity to help guide the organization through the transformation it began in 2016 to broaden its focus to system issues encompassing hardware, software, and design. My experience at Sonics straddling both the system-on-chip IP hardware and design software businesses should serve as a strong unifying asset in this leadership role on the board.”

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A Photo Montage of a RISC-V Evening to Remember

Tuesday, January 31st, 2017

Rainy winter weather didn’t deter anyone from the Open Source and the RISC-V processor panel Wednesday, January 18, hosted by the ESD Alliance at the Cadence facility in San Jose, Calif. Well, almost everyone. Rick O’Connor, executive director of the RISC-V Foundation, didn’t make it because a snowstorm closed the airport in Ottawa, Canada. Instead, he dialed in from there and gave the audience an overview of the RISC-V Foundation and was available to answer questions. Ted Speers, a member of the RISC-V Foundation board and head of Product Architecture and Planning for Microsemi’s SoC Group, amiably stepped in as his replacement.

The moderator was Jim Hogan of Vista Ventures, our long-time partner who works with Steve Pollock of AI-Pac on the regularly scheduled series like this one presented by our Emerging Companies Committee. Yunsup Lee, SiFive’s chief technology officer (CTO) and co-designer the RISC-V ISA and the first RISC-V microprocessors, offered a fascinating look at the open sources processor movement.

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Open Source and RISC-V Discussion January 18

Friday, December 23rd, 2016

riscv-logoPlease plan to join us Wednesday, January 18, for a discussion about Open Source and the RISC-V processor featuring Jim Hogan of Vista Ventures, Rick O’Connor, executive director of the RISC-V Foundation, and Yunsup Lee, SiFive’s chief technology officer (CTO). They will describe the path from inception to the open source RISC-V ecosystem, explore whether an open source architecture is appropriate for IoT processing needs and what that means for startups and innovation.

As you’ll hear them say, the number of IoT designs is growing at an astronomical pace. IoT devices are capable of sensing the real world. They are prevalent at the edge of the internet, communicating with an external host to process that real-world information. While there are advantages in performance and cost in processing the data locally, doing so requires significant processing capability at low-energy utilization. Systems designed with autonomous local intelligence have increased but require a microcontroller that can run software that takes energy. What emerged from the academic community are open source alternatives such as RISC-V from UC Berkeley that’s gained momentum over the last few years.
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Registration Opens for Phil Kaufman Award Dinner, More News from the ESD Alliance

Friday, December 9th, 2016

Registration opened this week for the Phil Kaufman Award Presentation and Dinner to honor Andrzej Strojwas, chief technologist at PDF Solutions and Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. AndrzejTrophyGraphic

I hope you’ll join us for a celebration that helps us kicks off 2017. The dinner will be held Thursday, January 26, at the Fourth Street Summit Center in San Jose, Calif., where we held the dinner paying tribute to Mentor Graphics’ Wally Rhines in 2015. The evening will begin with a reception and cocktails at 6:30 p.m. The dinner and award presentation will be run from 7:30 p.m. until 9 p.m. We have special entertainment planned that will challenge your senses!

Andrzej is being recognized with the award, presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA), for his pioneering research in the area of design for manufacturing (DFM) in the semiconductor industry.

Reservations are $175 per person for ESD Alliance and IEEE members or $250 per person for non-members. Seating is limited and we can accept R.S.V.P.s until Thursday, January 12. To reserve your seat at the 2016 Phil Kaufman Award Presentation and Dinner, visit our online registration.

Tables of 10 are available if your company be interested in sponsoring the event. Sponsorships will heighten a company’s visibility and brand exposure through positive publicity and promotion, and through signage and the program at the event. By sponsoring the dinner, your company is showing the community that it believes in the vibrancy of our industry and honoring those individuals who created it.

To find out more, visit our sponsorship page or call (408) 287-3322.
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A Busy December with REUSE 2016, Updates to Multi-Die IC Design Guide, New Member Outreach

Tuesday, November 22nd, 2016

While 2016’s coming to an end, it’s not quite over yet and the month of December will be busy for the ESD Alliance.

Our industry has one brand new event called REUSE 2016 that will take place Thursday, December 1. The ESD Alliance will be there, along with close to 40 other exhibitors.

REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. It will be held from 11 a.m. until 8 p.m. at the Computer History Museum in Mountain View, Calif. Admission is free.reuse_lg_fb

I’m moderating a conversation during REUSE with Lucio Lanza, managing director of Lanza techVentures, and Dan Rubin, general partner of Alloy Ventures. We’ll talk about the semiconductor IP market and IoT during the discussion titled, “IoT: Poised to offer huge growth opportunities for the global IP Business.”

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