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 Bridging the Frontier
Bob Smith, Executive Director
Bob Smith, Executive Director
Bob Smith is Executive Director of the Electronic System Design Alliance, formerly the EDA Consortium. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem. … More »

Welcome CAST and SoC Solutions, New Members of the ESD Alliance

 
April 25th, 2017 by Bob Smith, Executive Director

Please join me in welcoming two new members of the ESD Alliance –– CAST and SoC Solutions –– both of whom are semiconductor IP providers and intend to become active members of our SIP Working Group.

CAST of Woodcliff Lake, N.J., has 23 years of SIP experience and offers a range of production-proven SIP cores that include controllers and processors, compression, peripherals, interconnect and security, and encryption.

SoC Solutions from Suwanee, Ga., enables next-generation IoT and Machine to Machine (M2M) silicon devices by supplying processor-based IP and services to build innovative, low-power “connected” products.

According to Jim Bruister, SoC Solutions’ CEO: “The ESD Alliance is the all-important connection to the semiconductor design ecosystem. For a company like ours, there’s no better organization to belong to for both the networking opportunities and the Semiconductor IP Working Group that’s helping to define so many critical aspects of our market segment.”

“The IP market segment surpassed the historically larger CAE segment of EDA and needs focused, committed attention to a variety of business and technical requirements,” concurs Nikos Zervas, CEO of CAST. “The SIP Working Group offers a forum for companies to identify new growth areas and advance the most effective means to deliver our technology.”

Jim and Nikos are right. The SIP Working Group headed by Warren Savage, Silvaco’s general manager of IP, is creating a common methodology and best practices for fingerprinting, and an end-to-end solution for tracking and auditing soft and hard IP.

We’re delighted companies like CAST and SoC Solutions that also provide design services recognize the ESD Alliance as their voice to the semiconductor design ecosystem. As Jim Bruister pointed out, SoC Solutions values the Alliance’s range of networking opportunities, as does CAST. Both agree that the networking opportunities are another great reason for joining.

Has your company considered joining the ESD Alliance? Our roster of member companies is growing, especially in the IP market sector, an increasingly important area of the semiconductor industry. If your company would like to join or learn more about the membership options, please visit the ESD Alliance website to read more about the SIP Working Group, our other committees and ongoing initiatives. I’m available to answer questions as well and can be contacted at bob@esd-alliance.org

If you aren’t already, please follow the ESD Alliance at:

Website: esd-alliance.org

ESD Alliance Bridging the Frontier blog: http://bit.ly/2oJUVzl

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A Picture is Worth a Thousand Words –– Photos from the CEO Outlook!

 
April 20th, 2017 by Bob Smith, Executive Director

The semiconductor design ecosystem came out in force Thursday, April 6, for the CEO Outlook at Synopsys in Mountain View, Calif. It was a great crowd and an exceptional panel moderated by Semiconductor Engineering’s Ed Sperling. Thanks to Lip-Bu Tan of Cadence, Wally Rhines from Mentor, ARM’s Simon Segars and Aart de Geus at Synopsys for their insights and a lively discussion.

Our special guests that night were from the Dwight D. Eisenhower School for National Security and Resource Strategy, part of the National Defense University (NDU). The ESD Alliance hosts a yearly visit from the NDU students and organizes meetings with noted semiconductor companies in Silicon Valley to help educate them about our industry and its importance to the global electronics industry.

A picture is worth a thousand words, so I’ll dispense with a long blog and let the photos tell the story.

If you’re craving words to describe the evening, Peggy Aycinena wrote a blog filled with color and loads of details on EDACafe. It can be found at: http://bit.ly/2kjVajD

From left to right: ESD Alliance Board Chair Grant Pierce of Sonics, the ESD Alliance’s Julie Rogers, Wally Rhines, Aart de Geus, Paul Cohen of the ESD Alliance and Larry Disenhof of Cadence.

Ed Sperling of Semiconductor Engineering (at left) with panel members and ESD Alliance Board Member (from left to right) Lip-Bu Tan of Cadence, Wally Rhines from Mentor Graphics, ARM’s Simon Segars and Aart de Geus of Synopsys.

From left to right: Raul Campasano of Sage Design Automation, an ESD Alliance member company, Ed Chang, retired, and Steve Pollock from AiPac.

From left to right: Sherry Hess of and Ted Miracco of SmartFlow, both ESD Alliance member companies, and John Ennis of Cadence.


Read the rest of A Picture is Worth a Thousand Words –– Photos from the CEO Outlook!

Next Week’s CEO Outlook to Gaze at the Future, Bask in Industry’s Vitality

 
March 28th, 2017 by Bob Smith, Executive Director

The spectacular news this week from the ESD Alliance’s Market Statistics Service (MSS) that revenue increased 18.9 percent for Q4 2016 will be an exclamation point to next week’s CEO Outlook.

For example, revenue for Q4 in all four geographic regions –– Americas, Europe, Middle East and Africa, and Japan and Asia/Pacific –– increased 18.9 percent for Q4 2016 to $2455 million, compared to $2064.5 million in Q4 2015. All product categories saw fourth-quarter growth. In fact, CAE, Semiconductor IP, IC Physical Design & Verification and PCB/MCM reported double-digit increases. Another positive sign is employment is up 6.6% overall.

CEO Outlook attendees can expect to hear much more about industry opportunities for growth and challenges as Ed Sperling, editor-in-chief of Semiconductor Engineering, moderates the panel of four of our most visible CEOs and Alliance Board Members. They are: Aart de Geus, CEO at Synopsys, Lip-Bu Tan, president and CEO of Cadence, ARM’s CEO Simon Segars and Wally Rhines, chairman and CEO of Mentor Graphics and board sponsor for the MSS.
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ESD Alliance Brings Back CEO Outlook

 
March 17th, 2017 by Bob Smith, Executive Director

Please Note: With regrets, we are postponing the “Energy Policy and Strategy for the IoT Era,” the panel on the new energy rules for PCs from the California Energy Commission Thursday, March 23, due to unforeseen circumstances. Stay tuned for updates.

 After listening to our members who told us they missed the yearly CEO forecast, it’s a pleasure to let you know the ESD Alliance is bringing back an evening with the leaders of our industry. The 2017 CEO Outlook will be held Thursday, April 6, from 6:30pm until 8:45pm at Synopsys in Mountain View, Calif. A private reception for ESD Alliance members only to mingle with speakers will begin at 5:30pm.

Four of our industry’s most visible CEOs will discuss their views on the future of the system design ecosystem in what promises to be a wide-ranging and enlightening panel discussion. The four panelists for the evening are: Aart de Geus from Synopsys, Lip-Bu Tan of Cadence, ARM’s Simon Segars and Wally Rhines of Mentor Graphics. Each will share his views on where the semiconductor industry and system design ecosystem are heading, review trends and point out potential opportunities and danger signs ahead. After brief opening statements about the future of the industry, an interactive audience discussion will follow.
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March 23: An Evening on Energy Efficiency from the ESD Alliance and Sonics

 
March 7th, 2017 by Bob Smith, Executive Director

Fresh from our “Ride with the Verify Seven” evening co-hosted with ESD Alliance member company OneSpin during DVCon, we’re planning our next event with another member company –– Sonics –– Thursday, March 23.

The panel, “Energy Policy and Strategy for the IoT Era,” moderated by Grant Pierce, Sonics’ CEO and chairman of the Alliance board of directors, will outline new energy rules for PCs set by the California Energy Commission (CEC). A panel discussion will look at how these new rules affect the system design ecosystem and how the industry will adapt to them. 

The standards, primed to begin January 1, 2018 and roll out through July 2021, cover desktop computers, notebooks and laptops, small-scale servers, workstations and monitors, the top consumers of electricity in California. Estimates are staggering –– the state reports consumption of about 5,610 gigawatt hours of electricity or 3% of residential electricity use and 7% commercial. The CEC determined something needed to change, even though many manufacturers build seemingly energy-efficient products. The new standards are estimated to save 2,332 gigawatt hours per year and reduce utility bills by more than $370 million, enough energy to power about 350,000 California homes a year while reducing greenhouse gas emissions.

Please join us to learn more from a great line-up of panelists. For example, Dave Ashuckian, CEC’s deputy director of the Efficiency Division, and Pierre Delforge, director, High Tech Sector Energy Efficiency of the Natural Resources Defense Council (NRDC), will explain the new rules and regulations. They will describe how the standards came about and why they are necessary, how much energy they will save, when they will take effect and how they will be enforced.

Five other panelists will address what they mean for the system design ecosystem, including EDA, IP, embedded software and other technology vendors that supply products to PC system manufacturers. They will look at the implications for broader national and global energy efficiency standards for electronic products, particularly as they relate to the emerging IoT market. Those panelists include:

  • Ned Finkle, vice president of External Affairs at NVIDIA
  • Vic Kulkarni, ANSYS’ senior vice president and general manager of the RTL Power Business
  • Shahid Sheikh, director in Government and Policy Group with Intel Corporation
  • Lip-Bu Tan, Cadence’s president and CEO
  • Vojin Zivojnovic, founder and CEO of AGGIOS

As each provide their perspectives on opportunities for providers of goods and services in the system design ecosystem, attendees will learn about potential new technical innovations in design and manufacturing. They will get insights into what impact the rules will have on their companies’ as well as the semiconductor industry’s energy policies and strategies.

The panel will take place Thursday, March 23, beginning at 6 p.m. with networking, light snacks and drinks, at the San Jose City Hall Rotunda, a landmark building that serves as San Jose’s hub of civic and cultural activity. It is located at 200 East Santa Clara Street in San Jose, Calif.

Shireen Santosham, San Jose’s chief innovation officer, will offer opening remarks.

The panel is open free of charge to all ESD Alliance member companies. Non-members are welcome to attend for a fee of $40. More details and registration information can be found at: http://bit.ly/2mdHKpH

If we have enough interest, the Alliance may establish an Energy Policy and Strategy initiative and forge cross-industry alliances with like-minded industry organizations. To learn more or to become a member of the ESD Alliance, please contact me at bob@esd-alliance.org or visit our website at: www.esd-alliance.org

Missed one of the ESD Alliance’s events? Our Past Events page has photos and, in some cases, recordings of most of our events that go back as far as 1999. The page can be found at: http://bit.ly/2lxjQ9r

Photos from the Phil Kaufman Award Ceremony and Dinner, A Night to Remember

 
February 24th, 2017 by Bob Smith, Executive Director

The Super Bowl wasn’t the only festive event over the last few weeks! The Electronic Systems Design ecosystem honored Andrzej Strojwas as the 2016 Phil Kaufman Award recipient during an awards ceremony and dinner attended by close to 200 of us from the industry. It was held Thursday, January 26, at the Fourth Street Summit Center in San Jose, Calif.

Caption: Kaufman Award recipient Andrzej Strojwas (standing in the middle with his statuette), along with his extended family, PDF Solutions and Carnegie Mellon colleagues and graduate students.

For those of you who don’t know Dr. Strojwas, he is PDF Solutions’ chief technologist as well as the Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. He was recognized with the award for his pioneering research in the area of DFM in the semiconductor industry.

The Kaufman Award is presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA). For more information, check out: http://bit.ly/2l95wTO

As I did with the RISC-V event, I won’t try to recapture the evening when two of our favorite chroniclers Peggy Aycinena and Paul McLellan covered the evening so masterfully and neatly depicted the mood. (See the links to their blog posts below.) Instead, I’ll offer you a look at who was there through photos taken by the Alliance’s Paul Cohen and Julie Rogers and ace photographer Ross Mehan of Ross Mehan Photography. The video, produced by Andrew Mellows Video, will be available on the ESD Alliance website shortly.

Read the rest of Photos from the Phil Kaufman Award Ceremony and Dinner, A Night to Remember

ESD Alliance Bulletin: DVCon, New Member Helic, Upcoming Events

 
February 23rd, 2017 by Bob Smith, Executive Director

I promised in my last post a special blog post with great photos highlighting the Phil Kaufman Award Ceremony and Dinner January 26. It will go up Monday.

But first, the news that the ESD Alliance will exhibit at DVCon at the DoubleTree Hotel in San Jose, Calif. We’ll be in Booth #100 in the foyer, so please stop by if you’re attending.

During DVCon, we’re co-hosting with OneSpin Solutions a panel, “Ride with the Verify Seven,” moderated by Jim Hogan of Vista Ventures featuring six verification leaders who grew their companies from startup to medium-sized industry player. It will be held Monday beginning at 7 p.m., after the Booth Crawl, until 8:30 p.m. Light refreshments and drinks will be served.

Panelists include:

  • Andy Stein, Vice President of North American Sales from Avery Design Systems
  • Adnan Hamid, CEO at Breker Verification Systems
  • Phil Moorby, Chief Architect of Montana, a Phil Kaufman Award recipient presented to him by the ESD Alliance and IEEE CEDA for inventing the Verilog language
  • Raik Brinkmann, President and CEO of OneSpin, an ESD Alliance Member Company
  • Prakash Narain, President and CEO at Real Intent, an ESD Alliance Member Company
  • Rick Carlson, ESD Alliance Member Company Verific’s Vice President of Sales and advisor to seven early-stage startups

The event is open free of charge to all Alliance member companies and DVCon attendees. Non-members of the Alliance or anyone without a DVCon badge are invited to attend for a fee of $40. Registration information and more details on the event can be found at: http://bit.ly/2kNWx6T

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Come Ride with the Verify Seven, the Next-Gen Verification Leaders

 
February 17th, 2017 by Bob Smith, Executive Director

I’m now able to share with EDACafe readers the news about an exciting evening panel we’re co-hosting with OneSpinSolutions titled, “Ride with the Verify Seven,” during DVCon Monday, February 27.

It will be moderated by industry luminary Jim Hogan of Vista Ventures and features six well-known and readily recognizable verification leaders who grew their companies from startup to medium-sized industry player:

  • Andy Stein, Vice President of North American Sales from Avery Design Systems
  • Adnan Hamid, Chief Executive Officer (CEO) at Breker Verification Systems
  • Phil Moorby, Chief Architect of Montana, a Phil Kaufman Award recipient presented to him by the ESD Alliance and IEEE CEDA for inventing the Verilog language
  • Raik Brinkmann, President CEO of OneSpin
  • Prakash Narain, Real Intent’s President and CEO
  • Rick Carlson, Verific’s Vice President of Sales and advisor to seven early-stage startups

Read the rest of Come Ride with the Verify Seven, the Next-Gen Verification Leaders

Save the Date! The ESD Alliance/OneSpin Solutions Sponsor DVCon Event

 
February 13th, 2017 by Bob Smith, Executive Director

Please save Monday evening, February 27, during DVCon for an entertaining but informative and inspiring panel discussion with today’s emerging verification leaders. Sponsored by the ESD Alliance and OneSpin Solutions, the discussion will be moderated by the always enthusiastic Jim Hogan who will tease out how they are succeeding in a market where much larger competitors also participate.

We plan to start right after the DVCon Expo Booth Crawl that runs from 5-7pm. We’ll have drinks and snacks and there will be planey of opportunity to network. DVCon will be held at the Doubletree Hotel, San Jose, Calif.

Watch this space for more details on who’s participating in the discussion and the room where it will be held.

Grant Pierce to Chair ESD Alliance Board of Directors

 
February 9th, 2017 by Bob Smith, Executive Director

I’m pleased to be able to announce that Grant Pierce, CEO of Sonics, Inc., was elected by the ESD Alliance Board of Directors to serve as chairman. Grant and I have had the opportunity to work together on several Alliance projects and I welcome the chance to work more closely with him. He is an active board member, whose varied industry experience and well-honed skillset will help us forge ahead.

Grant Pierce

Grant is quoted in our news release as saying: “It is an honor and a privilege to be named chairman of the ESD Alliance by my peers on the board. This is a great opportunity to help guide the organization through the transformation it began in 2016 to broaden its focus to system issues encompassing hardware, software, and design. My experience at Sonics straddling both the system-on-chip IP hardware and design software businesses should serve as a strong unifying asset in this leadership role on the board.”

Read the rest of Grant Pierce to Chair ESD Alliance Board of Directors

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