Bridging the Frontier
Bob Smith, Executive Director
Bob Smith is Executive Director of the ESD Alliance responsible for its management and operations. Previously, Bob was senior vice president of Marketing and Business Development at Uniquify, responsible for brand development, positioning, strategy and business development activities. Bob began his … More »
February 19th, 2018 by Bob Smith, Executive Director
San Jose should be hopping next week as chip design verification enthusiasts from all over arrive for the annual DVCon conference and exposition that runs Monday through Thursday, February 26-March 1, at the DoubleTree Hotel.
If you plan to attend, stop by our tabletop in the foyer directly across from the entrance to the exhibit area. You can find out about the ESD Alliance’s charter, programs, initiatives and ongoing events. Exhibitors and attendees can pick up copies of its latest newsletter and giveaways for members and companies interested in joining.
While Monday’s a full day of tutorials, attendees will stick around for the DVCon Expo and Reception that will be held from 5 p.m. until 7 p.m. The exhibit floor is open Tuesday, February 27, and Wednesday, February 28, from 2:30 p.m. until 6 p.m. as well. The tutorial program continues Thursday.
Attendees will find a good number of our members on the exhibit floor. They include:
Altair Engineering, Booth #404
AMIQ EDA, Booth #405
Blue Pearl, #701
Breker Verification Systems, Booth #304
Cadence, Booth #702
Mentor, a Siemens Business, Booth #1101
OneSpin, Booth #902
Real Intent, Booth #402
Sigasi, Booth #601
Synopsys, Booth #101
Verific, Booth #505
Many of these same companies will offer presentations, tutorials, lunches and collocated events, and may be part of the poster sessions. One or two will be represented on one of Wednesday’s panels. Synopsys’ Christopher Tice will give the keynote titled, “Industry’s Next Challenge: The Petacycle Challenge.” That will be held Tuesday at 1:30 p.m.
DVCon is sponsored by the industry initiative Accellera. Exhibits-only registration is free and includes the keynote and panels. For details on the full-conference registration, go to the DVCon website at: www.dvcon.org
We look forward to seeing you at DVCon and, if your company is not a member, we welcome the chance to explain why your company should join the ESD Alliance. If you won’t be at DVCon this year, please visit the ESD Alliance website to read about our committees and other ongoing initiatives, or contact me for more specifics on ROI or other justifications for joining. I can be reached at firstname.lastname@example.org
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February 11th, 2018 by Bob Smith, Executive Director
The Electronic System Design ecosystem community turned out in force for the Phil Kaufman Award Ceremony and Dinner honoring Dr. Rob A. Rutenbar, senior vice chancellor for Research at the University of Pittsburgh. The evening, hosted by the ESD Alliance and the IEEE Council on EDA (CEDA), was sponsored by ACM SigDA, Arm, Cadence, Mentor, a Siemens Business, PDF Solutions and Synopsys.
I’ll post more photos in a few days. Meanwhile, here are just a few highlighting the special evening.
January 24th, 2018 by Bob Smith, Executive Director
What’s this about an “alley” on the DAC floor this year? It’s true –– the Design Infrastructure Alley –– is for exhibitors and presenters to highlight the information technology infrastructure, a fundamental element that allows the creation and design of complex electronic systems and components.
We all hear about the achievements of chip design groups. They wouldn’t be able to work their magic, though, without an army of professionals that make sure that the design environment is optimized for fast turnaround and up and running 24×7. The “army” is made up of IT and design specialists who apply and manage sophisticated hardware and software to keep computing bandwidth, availability, licensing, security and storage in good working order. Without this group and their powerful tools that allow complex systems to be created and designed, new innovation would never happen.
The Design Infrastructure Alley is the brainchild of Derek Magill, senior manager of IT at Qualcomm, and the ESD Alliance’s Paul Cohen and me. Derek also is chair of CELUG (Centralized Enterprise License User’s Group) that provides enterprise user input to the ESD Alliance’s license management committee. Together with DAC, we invite companies that are part of this vital and expanding area of electronic product design to participate and exhibit in the Design Infrastructure Alley.
January 19th, 2018 by Bob Smith, Executive Director
Anyone who joins us for the Phil Kaufman Award ceremony and dinner knows attendees are the “who’s who” of the electronic system design ecosystem and this year’s evening will be no different. Come to “see and be seen” at The GlassHouse in San Jose, Calif., Thursday, February 8, for the Phil Kaufman Award ceremony and dinner. We will honor Dr. Rob A. Rutenbar, senior vice chancellor for Research at the University of Pittsburgh, the recipient of the 2017 Phil Kaufman Award for Distinguished Contributions to Electronic System Design.
If you attend, you’ll rub shoulders with executives from Arm, Cadence, Mentor, a Siemens Business, PDF Solutions, Synopsys and ACM SigDA who are sponsoring the evening presented by the ESD Alliance and the IEEE Council on EDA (CEDA). Attendance is open to member companies at a substantial discount. Of course, you don’t need to be a member to attend. Registration is open and information can be found at: http://bit.ly/2mt9XId
Everyone attending the dinner will help us celebrate the positive news coming from our most recent Market Statistics Service (MSS) report. As just noted in our Q3 2017 MSS report, industry revenue was up 8 percent over Q3 2016. Another positive sign –– employment in the system design ecosystem is up almost 10% when compared to Q3 2016.
The MSS newsletter can be found at: https://goo.gl/qd5bvF. Naturally, the complete quarterly MSS report has much more information, containing detailed revenue data broken out by both categories and geographic regions. The report is available to member companies of the ESD Alliance, another excellent reason to join.
About Dr. Rob Rutenbar
Rob Rutenbar’s contributions are significant and include founding multiple startups, including Neolinear, an analog tool company now part of Cadence. As an academic researcher at CMU, he pioneered a range of models, algorithms and tools for analog IC designs. During his tenure at the University of Illinois, he reworked his long-running CMU course, “VLSI CAD: Logic to Layout,” into the first Massive, Open, Online Course (MOOC) on EDA, providing training to thousands of engineers.
He’s a credit to the industry and is well deserving of the Phil Kaufman Award. Please join us in feting Dr. Rob Rutenbar. Everyone at the ESD Alliance and IEEE CEDA looks forward to seeing you February 8. Registration is open until Friday, January 26. Details are available at: http://bit.ly/2mt9XId
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January 11th, 2018 by Bob Smith, Executive Director
The ESD Alliance events calendar kicks-off 2018 with a special evening honoring Dr. Rob A. Rutenbar, senior vice chancellor for Research at the University of Pittsburgh. Dr. Rutenbar is the recipient of the 2017 Phil Kaufman Award for Distinguished Contributions to Electronic System Design.
The beautiful GlassHouse serves as the location in downtown San Jose, Calif., for the Phil Kaufman Award ceremony and dinner Thursday, February 8, beginning at 6:30 p.m. We hope you will be able to join the ESD Alliance and the IEEE Council on EDA (CEDA) in celebrating Dr. Rutenbar’s many achievements. Registration opened today and can be found at: http://bit.ly/2mt9XId Please register now!
Dr. Rutenbar is a popular, versatile and entrepreneurial member of our community with contributions ranging from algorithms and tools for analog and mixed-signal designs to founding multiple startups, including Neolinear, a successful analog tool company. As an academic researcher at CMU, he pioneered a range of models, algorithms and tools for analog IC designs. During his tenure at the University of Illinois, he reworked his long-running CMU course, “VLSI CAD: Logic to Layout,” into the first Massive, Open, Online Course (MOOC) on EDA, providing training to thousands of engineers.
Special thanks to Arm, Cadence, Mentor, a Siemens Business, Synopsys and ACM SigDA for sponsoring the evening. We have a few more sponsorships available. If your company is interested, sponsorship information can be found at: http://bit.ly/2BebB9W.
Many of our community members warmly remember Phil Kaufman for whom the Phil Kaufman Award was named. An industry pioneer who turned innovative technologies into commercial businesses that benefit electronic designers even today, he was president and CEO of Quickturn Systems (now Cadence) at the time of his death in 1992. Prior to Quickturn, he was CEO of early and influential EDA vendor Silicon Compiler Systems, now part of Mentor.
The award, first granted in 1994, is presented to individuals who have had a demonstrable impact on the field of electronic system design through technology innovations, education/mentoring, or business or industry leadership. Last year’s recipient was Andrzej J. Strojwas, Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University, recognized for his pioneering research in the area of design for manufacturing in the semiconductor industry.
A reminder that attendance at the Phil Kaufman Award ceremony and dinner, always a great networking event, is open to member companies at a substantial discount. Please visit the registration page at http://bit.ly/2mt9XId for more information. If your company would like to join the ESD Alliance, join now and join us for the ceremony and dinner.
Please visit the ESD Alliance website (www.esd-alliance.org) to read why so many companies in the electronic system design ecosystem are members. You can contact me at (email@example.com) for more information.
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December 18th, 2017 by Bob Smith, Executive Director
Andrzej J. Strojwas, Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University, was feted at the Phil Kaufman Award dinner and ceremony in late January, a great way to kick-off the year.
However, our first event of 2017 was a panel on RISC-V, a captivating discussion on the possibilities of an open source processor. It was bookended two weeks ago with a panel on cognitive computing at San Jose State University, both organized and moderated by Jim Hogan of Vista Ventures. That evening closed out our 2017 events calendar. We are grateful to Jim for his continued support of the ESD Alliance and for bringing to the forefront new topics our community wants to learn about.
The CEO Outlook in April was deemed a success and we’ve been encouraged to do it again in 2018. Another successful evening was “Empowering Leadership with WIT and WISDOM” co-hosted by ANSYS, the ESD Alliance and SEMI. Julie Rogers, our director of marketing and operations, wrote a recent blog about it in this space.
Photos of all the 2017 events are found on the ESD Alliance website at: www.esd-alliance.org
We had plenty of news on the member front. Grant A. Pierce, CEO of Sonics, was elected by the Board of Directors to serve as its chairman, while Mentor was acquired by Siemens, and Runtime became part of Altair. Later in the year, Mentor, a Siemens Business, acquired Solido. We welcomed several new member companies this year, including CAST, EDDR Software, Helic and SoC Solutions, now part of Silvaco.
December 11th, 2017 by Julie Rogers
A large and enthusiastic crowd greeted five high-powered women panelists as they took the stage two weeks ago to talk about “Empowering Leadership with WIT and WISDOM” with Ann Steffora Mutschler of Semiconductor Engineering. The memorable evening was co-hosted by ANSYS, the ESD Alliance and SEMI at SEMI’s new headquarters in Milpitas, Calif.
Ajit Manocha, SEMI’s president and CEO, offered a welcome and conveyed the organization’s commitment to advancement in the workplace as attendees began settling in. He suggested that a better title for the evening would be “WIT and WISDOM with Women in the Workplace,” that got plenty of smiles and heads nodding in agreement.
I’m sure audience members, a mix of men and women, will take heed to the pearls of wisdom from the empowering 90 minute-long discussion. Ann asked each panelist to focus on an area, from personal branding and leadership to negotiation, networking and mentoring. She captured valuable insights each of the women made in a great wrap-up article that includes photos of the evening. It can be found at: http://bit.ly/2Apad0C. A recording of the panel is posted on the ESD Alliance website, along with additional photos, at: http://bit.ly/2jc5ffQ.
November 21st, 2017 by Bob Smith, Executive Director
Editor’s Note: Filling in for Bob Smith, executive director of the ESD Alliance, is Paul Cohen, its member of the technical staff.
Two upcoming events co-hosted by the ESD Alliance, “Empowering Leadership with WIT and WISDOM” and “Artificial Intelligence and Convolution Neural Networks,” are only days apart from one another and seem to tackle decidedly different topics. Or do they?
For “Empowering Leadership with WIT (Women in Technology) and WISDOM,” a panel of executives from the technology sector will explore various career choices for men and women Tuesday, November 28, at SEMI in Milpitas, Calif.
“Artificial Intelligence and Convolution Neural Networks” Monday, December 4, at San Jose State University (SJSU) will feature a panel discussion on the systems companies are building to gather data and process it to drive business operations.
November 1st, 2017 by Bob Smith, Executive Director
Mark your calendars and register today for “Empowering Leadership with WIT (Women in Technology) and WISDOM,” a panel of executives from the technology sector who will explore various career choices for men and women. It will be held Tuesday, November 28, at SEMI in Milpitas, Calif., and begins with dinner and refreshments at 6 p.m. The panel discussion will start at 6:45 p.m. and conclude at 8:30 p.m.
Your hosts for the evening are the ESD Alliance, ANSYS, SEMI and Semiconductor Engineering, along with NetSpeed Systems, Samsung, Stanford Health Care and Tribal Ventures.
You can expect a lively and topical discussion, moderated by Ann Steffora Mutschler, executive editor/EDA at Semiconductor Engineering, that will include tips and insights into personal branding, leadership, negotiation, networking and mentoring. Its aim is to help you develop your personal strategy to achieve your goals, whether you are starting out, seeking your next opportunity or trying to proactively navigate your career.
October 10th, 2017 by Bob Smith, Executive Director
We hope you’ll be able to attend the second evening in a series on The Cognitive Era titled, “Preparing for the Cognitive Era: Education, Occupation and You,” offered by Vishal Kapoor, a founding principal at three legged stool.
The evening, presented by Jim Hogan and co-hosted by the ESD Alliance and San Jose State University (SJSU), will be held Wednesday, October 18, beginning at 6:30 p.m. with light refreshments and networking. Vishal’s talk will start at 7 p.m. and run until 8:30 p.m.
Vishal will share his perspective on the dynamics of the Cognitive Era and assess the major shifts in education, occupation and understanding of the practical dynamics. He will challenge audience members to think about how the Cognitive Era is affecting them and whether they are prepared for it.
The event, open and free of charge, will be held at SJSU’s Diaz Compean Student Union Theater, 211 South 9th Street, San Jose, Calif. To register, go to: http://bit.ly/2xar60S