Next up in our series of predictions is the astute insight of Mike Demler, Senior Analyst with The Linley Group & MICROPROCESSOR report, and former EDA & Chip Design news analyst.
“It’s all about the ecosystem triad: EDA + foundry + IP. Cadence and Synopsys continue to evolve more in the IP direction, and there is really not much to say about the tools that hasn’t been said for a long time —just make it all work together! Redundant “standards” and artificial barriers to interoperability cost the semiconductor industry by lowering productivity. This is the problem with the disaggregated model. Back in the days when “real men” had fabs, companies could develop complete design flows without such obstacles.
The triad needs to work together to get over the stall inMoore’s Law at 28nm. Foundries are incurring delays in getting to 16/14nm FinFETS, and almost nobody is going to use 20nm. The chip industry needs an overall lower-cost solution in order to make sub-28nm processes economically viable. Forget 3D ICs, those will be niche products for a long time, about as popular as 3D TV.