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Posts Tagged ‘Tech-On’

Renesas on SpyGlass Physical

Monday, August 20th, 2012



Yasushi Ozaki, Director of Engineering Department overseeing product design and Development, at Renesas, spoke at the Atrenta Technology Forum First inYokohama.  This is Tech-On’s coverage of his presentation and his evaluation of SpyGlass Physical, which is an EDA tool for estimating chip area and logic depth at the RTL stage:





Lee PR does work for Atrenta


S2C: FPGA Base prototyping- Download white paper

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