Posts Tagged ‘Synopsys’
Wednesday, January 18th, 2012
One lingering question for 2012 is what will become of the Magma back-end platform? I predict that Synopsys will phase out the Magma Talus platform in favor of ICC. Why? It makes no sense for Synopsys to continue to field and support two different systems although it is likely that there will be some transfer of technology into ICC. Converting the existing Talus user base over to ICC is no small task and will likely take several years to complete as well as require incentives and utilities to move the existing base over to the Synopsys platform.
Timing verification is another story. Synopsys will capitalize on the acquisitions of Extreme and Magma to leverage the technologies in those products to develop and deliver the next generation PrimeTime platform. Once they complete this, they will have re-solidified their position as the industry golden standard in static timing verification.
It will be very interesting to see how the consumer-driven SoC market will evolve. SoCs used to be comprised of a processor, memory, various IP blocks, and the on-chip infrastructure needed to support them such as clock, power and communications channels. Now SoCs have multiple processors, large numbers of IP blocks, multiple on-chip communications channels and multiple memories. In essence, today’s SoCs are comprised of multiple SoCs as we used to define them.
The 2012 SoC will beget big challenges in design and even more so in verification. IP will become more important. And even though hardware performance and power will matter, system design and software will become the differentiating items.
SoC system design and verification will be especially active, because it is what the system does that really counts. (After all, the point of building an SoC is to deliver a winning end product.) To a great extent that will require a huge software and verification effort — under the schedule pressures that come from a hugely competitive consumer products market.
Tuesday, December 13th, 2011
Mike Demler of EE Daily News raises intriguing questions about the price of the Magma buyout. Seems too low, says Demler. And there’s more to come.
Monday, March 28th, 2011
Continuing with my conversation with Tom Kozas, president of CADmazing Solutions, I asked him about a hypothetical scenario:
Ed: So Tom, what would happen if for some reason, the big three EDA vendors all went away? So instead of Cadence, Mentor, Synopsys, the biggest three would be Magma, Apache? Atrenta?
Tom: I think this raises even more questions.
Ed: Hmmm…interesting. What questions?
Tom: Several come to mind: Would this mean renewed growth for the industry? Would the fundamentals change that encourage investment in new startups? Would the design flows become more or less integrated, collaborative, and global?
Ed: Ok, good questions to ponder. So what would be THE big issue?
Tom: The “Silicon” in Silicon Valley is missing. Without investment in new semiconductor startups, growth simply won’t happen. Virtually all new design starts are happening within the big systems and semiconductor companies which means the only way to grow an EDA company, is to steal market share.
But would this translate to increased value for the remaining EDA companies in the eyes of the financial community? What’s interesting about this hypothetical is, even though it would put the remaining EDA companies in a position to take advantage of this opportunity they might not be able to.
Ed: Just to play devil’s advocate, why wouldn’t that next set of players, whoever they are, be able to take advantage of the sudden disappearance of the big three? And who do you consider to be that next set of players?
Tom: Good questions. But let me respond by saying what they will need to provide.
So, the next big three will have products that have great user interfaces, provide online collaboration, and be part of a new ecosystem that enables innovation. The industry already has advanced technology but needs graphical and command-line interfaces that exploit the online design environment.
Second, designers don’t necessarily sit in the same building but often have to work on the same problem. For example, two or more designers should be able to share the timing database and bring up the same timing path without having to rerun static timing analysis and do it within minutes no matter where they are in the world.
Finally, the current EDA ecosystem is in the dark ages, there needs to be a new model that facilitates new algorithm and tool development with a reward system.
Ed: Tom, thanks again for your insights.
Tuesday, March 22nd, 2011
Ken Brock is the Product Marketing Manager for DesignWare Logic Libraries at Synopsys. Ken shared with us here his view of the trends he sees for the future of semiconductor IP.
What Does the Future Hold for Semiconductor IP?
The marketplace for semiconductor IP (SIP) continues to grow at double digit rates. According to Gartner Dataquest, the number of third-party semiconductor design IP blocks in an average chip design will double from the current level and the SIP market will reach $2.3B in 2014. IBS and Semico believe the SIP market will be greater than $3 billion in 2014.
We see six major trends in IP:
- Convergence: The increased demand for “Smart” consumer electronics is driving more features and functionality into a single device such as the latest craze in tablets shown at this year’s Consumer Electronics Show (CES). This trend is causing significant changes in SoC designs in areas such as power and performance requirements that drive technology node migrations, and in increased clock frequencies to keep up with bandwidth needs.
- Core versus Context: Does this function differentiate the SoC? Interfaces like PCI Express® and USB have to work but they don’t generally differentiate the SoC. As an IP vendor, we see many different applications spaces for our IP and we have to ensure that IP works over a broad range of configurations and products.
- Fab-outsourcing: More outsourcing of manufacturing means more opportunity for customers to use off-the-shelf IP to meet their design requirements, and more demand for IP vendors to create high-quality IP on the most advanced process nodes.
- Power, Performance, Area: As many semiconductor designs compete for the key sockets, having the fastest performance, lowest power and smallest area is often a key differentiator of the design with respect to processor performance, battery life, packaging cost and silicon cost. Choices of foundation IP (memory and logic) providers make a big difference between winners and also-rans.
- Consumer-driven schedules: Shorter time-to-market and more features means that designers need to de-risk schedules by using high-quality IP solutions that have been proven time and time again in the market place.
- Expense control: It is often less expensive for companies to buy third-party IP than to develop it themselves. This is particularly true in advanced nodes where the complexity of IP development increases rapidly with increasing data rates, restricted design rules and increasing variability. As an example, our estimate is that a 28nm standard cell and memory IP platform is at least five to 10 times as complex to design and verify as compared to a similar platform at 40nm.
With these trends as the backdrop, we see significant shifts in the SIP market as it continues to evolve during the next five years:
- Most SoCs will have about 70 to 80 percent of their functionality in reused IP (internal and/or 3rd party). The majority of these IP blocks will be memories with thousands of instances per chip all connected with a variety of standard cell configurations. Optimized standard cells and memories can significantly impact the performance, power and area of a SoC.
- Individual IP products will yield to more complex IP subsystems. These subsystems will include application-specific blocks and software. IP integration services will become increasingly important to validate the IP in the system context.
- Multi-core designs will drive increasingly complex architectures. A virtual prototype of the IP and the larger SoC will enable earlier and more efficient development of application software and middleware.
This is a pivotal time for the semiconductor IP industry as companies strive to develop the best solutions to help designers accelerate their time from concept to implementation. These solutions generate value throughout the design chain by accelerating hardware/software integration and systems validation, allowing efficient SoC architecture exploration and optimization, creating and optimizing functional blocks, and using high-quality semiconductor IP. Designers are turning to trusted third-party SIP solutions to help integrate advanced functionality with the least amount of risk. Winners will choose wisely.
Tuesday, March 8th, 2011
I recently grabbed coffee with Tom Kozas, President of Cadmazing Solutions. Since Tom’s staff works with a variety of domestic and international electronic designers spanning many industries, he sees a lot of different attitudes toward design tools. So I asked him:
Ed: So Tom, what about EDA in the clouds? Do your clients see that as desirable? Even viable?
Tom: It all depends on who is realizing the value.
Ed: When you say “realizing the value,” what do you mean?
Tom: OK, good point. EDA vendors have a completely different reality of their product value than do their customers. The EDA vendors believe that their product provides “absolute” value while EDA customers only see incremental product value. At CADmazing we deal with this reality with every customer and vendor we engage with.
Ed: Why the vast discrepancy?
Tom: Well, it’s the customer that commits the extra time and effort to go from incremental to absolute value for the complete design flow. As for EDA in the cloud it won’t fix the EDA industry.
Ed: No? Why is that?
Tom: Large customers already have their own clouds accessed through virtual private networks. So if a customer’s design environment included tools from each of the three top vendors, would this mean they would have to log into three different clouds?
Ed: Well, would the EDA customers then create their own cloud interface that all EDA tools would have to work? Or that the big three could create a standard cloud interface?
Tom: I just don’t see this type of collaboration happening among the top three EDA vendors. The industry would need something like an “Open Cloud” initiative that enables customers to have access to any EDA tool they want, especially from EDA startups – once the world comes back to its senses and starts funding them again.
Ed: So what’s your take on when EDA will be in the cloud?
Tom: Some EDA companies are already offering their products on the cloud. EDA companies will need to be careful that they are not creating a solution looking for a problem.
If EDA vendors want to successfully offer their tools and services on the cloud, they will need to provide an advantage that increases their customers’ business success. A technical and/or business advantage that goes way beyond outsourcing compute cycles.
Ed: Tom, thanks for your take on the EDA cloud.
Tom Kozas is President and principal consultant of Cadmazing Solutions www.cadmazing.com and has worked for years in engineering and marketing at EDA startups – such as Monterey – and established companies – such as Hughes Aircraft, Cadence, Compass. Cadmazing provides IC CAD development & implementation services for analog, digital, and mixed-signal system-on-a-chip (SoC) technology and full-custom designs. Tom’s email is: tomk@Cadmazing.com.
Monday, July 12th, 2010
The pre-DAC acquisitions of Denali and Virage drastically realign the core of the EDA industry. When IP first came on the scene here in the US, (I think 3Soft was the first IP company I saw), many people figured that IP would become another form of delivery for chip designs – and that they would come from the semiconductor companies.
The EDA executives’ explicit remarks about how IP is key to their continued growth could turn EDA into an industry of IP haves and IP have nots.
How does this EDA realignment affect customers? We asked Atrenta vice president of marketing and industry voice Mike Gianfagna, ” What does the EDA industry realignment mean for customers?”
Here’s what he said:
Realignment can mean two things that are related, but a bit different.
One form of realignment we’re seeing is the IP market merging into the EDA market. This is definitely good for IP customers. Effective IP reuse requires a blend of quality, highly validated IP and a good reuse methodology. The methodology need is for both authoring IP to be reusable and implementing the reuse itself. EDA is a good place to bring all this together. Most larger EDA companies understand what it takes to deliver high quality, validated designs. They also understand what a reuse methodology should include. A lot of the smaller IP shops don’t have this perspective.
Another realignment is the “annexation” of embedded software into EDA. Synopsys is validating this trend with their buying spree, and Cadence is validating the trend with their EDA360 proposal and some buying, too. This is also good for the customer. If software development teams can help to drive the silicon creation process, we are going to see some new killer apps emerge as a result.
What do you think about the combination of IP and EDA? Let us know in the “comments” section.
– end –
Saturday, June 12th, 2010
We asked three EDA figures to comment on how the Synopsys purchase of Virage would impact the EDA and IP industries. Here’s what they said.
This acquisition puts Synopsys squarely in the front of the pack as far as IP suppliers go. This trend could be quite significant. Successful IP reuse is a combination of the right EDA tools, best practices methodology and well-designed IP. The EDA vendor is a pretty good place for all that to come together. ARM remains the exception to this rule, and several other rules for that matter.
Vice President, Marketing
I don’t see how this doesn’t make Synopsys a competitor with ARM on physical IP and ARC processor. ARM should start feeling like it is getting surrounded by Synopsys.
With EDA trying to expand its scope and grow beyond its traditional boundaries (see EDA360), and with small and medium size IP vendors struggling to grow, basic economy forces are pushing this trend.
Synopsys has already been a formidable IP player and Cadence now entered it with its recent acquisition of Denali.
There are still plenty of smaller IP players so we’ll see further consolidation playing out. The IP segment has been trying to define and position itself between EDA and semiconductors. We all wondered if IP would become an intrinsic part of the semiconductor industry, the EDA industry, or stand on its own. These days we clearly see that the IP pendulum has shifted toward EDA.
The outlier is of course ARM which is a different beast, in some ways closer to semiconductors: i.e., look at how ARM competes with Intel. With a market cap equivalent to Synopsys and Cadence put together, ARM is simply too big for that.
– end –
Wednesday, December 30th, 2009
(Liz Massingill was fortunate enough to snag Harry Gries … the ASIC Guy for an interview on a rainy Friday morning. Here’s what they had to say.)
Liz: Harry, why do you blog?
Harry: There’s really 2 parts to that … why did I start and why do I keep doing it. I was having lunch with a good friend a few years ago, who is also a blogger, and I was sharing my opinions about some subject when he said “you should have a blog.”
I always liked to write and always had an opinion, so I said, “what the heck.” It was right before SNUG (Synopsys Users Group) so I also thought it would be a good way to do some personal marketing since I’m an independent consultant. So I got the blog up just in time for SNUG.
Liz: Was your first blog successful?
Harry: When I first started writing the blog, I told a few friends and colleagues about it and they subscribed and commented. Then, one day, I got a comment from someone I did not know at all. That was the first time I knew that people were reading this other than my friends.
Liz: That first comment must have gotten the adrenaline going. So why do you continue to blog?
Harry: As for why I keep going, I think I actually get a lot out of writing it. It keeps me plugged into what is going on in the industry. Also, I’ve met people through the blog that I never would have had a chance to know.
One example: There was a press release related to something one of the big 3 EDA companies was doing for training for their consultants. I wanted to write something about it on my blog so I emailed the VP of Consulting, who I did not know, and he answered back and did the interview. I never would have been able to do that without the blog.
Also, I’ve found that the people who read my blog are pretty influential, so it’s good to know them as well.
Liz: It never ceases to amaze me how small the internet has made our world. Who is your audience?
Harry: That’s a good question. With RSS, you never really know exactly who is reading. However, from the comments I get, from the people that follow me on Twitter, and from the analytics, I can tell that there are a lot of people in EDA companies, especially sales and marketing types.
Liz: Do you have Google analytics to find out how many hits you get?
Harry: Analytics helps, but not in the way you might think. I’m more interested in learning how people find my blog rather than who they are. I can tell what keywords they might have used in Google or what links they came from and that helps me to understand what they are looking for as valuable content.
Liz: Can you give me an example?
Harry: Well, lemme pull up my analytics right now: I just did a quick scan and noticed that “verification” and “FPGA” were used as search terms several times to find me. So I might write my next blog post on “FPGA verification.”
Liz: Then it is very useful.
(End of Part One.)